#endif
if (assert && devsel != 0) {
- // supress signal to cardbus
+ // suppress signal to cardbus
au_writel( 0x00000002, SYS_OUTPUTCLR ); // set EXT_IO3 OFF
}
else {
jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
{
/*
- * Convert jiffies to nanoseconds and seperate with
+ * Convert jiffies to nanoseconds and separate with
* one divide.
*/
u64 nsec = (u64)jiffies * TICK_NSEC;
jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
{
/*
- * Convert jiffies to nanoseconds and seperate with
+ * Convert jiffies to nanoseconds and separate with
* one divide.
*/
u64 nsec = (u64)jiffies * TICK_NSEC;
}
}
- /* Run the syscall at the priviledge of the user who loaded the
+ /* Run the syscall at the privilege of the user who loaded the
SP program */
if (vpe_getuid(tclimit))
#endif /* CONFIG_SGI_IP27 */
/*
- * arch_mem_init - initialize memory managment subsystem
+ * arch_mem_init - initialize memory management subsystem
*
* o plat_mem_setup() detects the memory configuration and will record detected
* memory areas using add_memory_region.
*
* At this stage the memory configuration of the system is known to the
- * kernel but generic memory managment system is still entirely uninitialized.
+ * kernel but generic memory management system is still entirely uninitialized.
*
* o bootmem_init()
* o sparse_init()
static atomic_t ipi_timer_latch[NR_CPUS];
/*
- * Number of InterProcessor Interupt (IPI) message buffers to allocate
+ * Number of InterProcessor Interrupt (IPI) message buffers to allocate
*/
#define IPIBUF_PER_CPU 4
if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
if (type == SMTC_CLOCK_TICK)
atomic_inc(&ipi_timer_latch[cpu]);
- /* If not on same VPE, enqueue and send cross-VPE interupt */
+ /* If not on same VPE, enqueue and send cross-VPE interrupt */
smtc_ipi_nq(&IPIQ[cpu], pipi);
LOCK_CORE_PRA();
settc(cpu_data[cpu].tc_id);
return;
if (!cpu_has_vint)
- panic("SMTC Kernel requires Vectored Interupt support");
+ panic("SMTC Kernel requires Vectored Interrupt support");
set_vi_handler(MIPS_CPU_IPI_IRQ, ipi_irq_dispatch);
/*
* Do the probing thing on R4000SC and R4400SC processors. Other
* processors don't have a S-cache that would be relevant to the
- * Linux memory managment.
+ * Linux memory management.
*/
switch (c->cputype) {
case CPU_R4000SC:
}
/*
- * hub_pio_init - PIO-related hub initalization
+ * hub_pio_init - PIO-related hub initialization
*
* @hub: hubinfo structure for our hub
*/