if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
if (strncmp(device_id, "BFIN_UART", 9) == 0)
dma_ch[channel].regs->peripheral_map |=
- (channel - CH_UART2_RX + 0xC);
+ ((channel - CH_UART2_RX + 0xC)<<12);
else
dma_ch[channel].regs->peripheral_map |=
- (channel - CH_UART2_RX + 0x6);
+ ((channel - CH_UART2_RX + 0x6)<<12);
}
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
#include <linux/serial_8250.h>
&serial8250_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_KEYBOARD_OPENCORES) || defined(CONFIG_KEYBOARD_OPENCORES_MODULE)
&opencores_kbd_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
static struct platform_device bfin_sport0_uart_device = {
.name = "bfin-sport-uart",
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
&bfin_sport0_uart_device,
&bfin_sport1_uart_device,
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#define PATA_INT 55
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
static struct resource isp1362_hcd_resources[] = {
{
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
&isp1362_hcd_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
static struct platform_device bfin_sport0_uart_device = {
.name = "bfin-sport-uart",
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
&bfin_sport0_uart_device,
&bfin_sport1_uart_device,
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
static struct platform_device *stamp_devices[] __initdata = {
#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
+
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
};
static int __init stamp_init(void)
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR2
+ {
+ .start = 0xFFC02100,
+ .end = 0xFFC021FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR3
+ {
+ .start = 0xFFC03100,
+ .end = 0xFFC031FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
static struct resource smsc911x_resources[] = {
{
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
&bf54x_lq043_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ .start = 0xFFC02000,
+ .end = 0xFFC020FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR2
+ {
+ .start = 0xFFC02100,
+ .end = 0xFFC021FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR3
+ {
+ .start = 0xFFC03100,
+ .end = 0xFFC031FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
static struct resource smsc911x_resources[] = {
{
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
&bf54x_lq043_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
#define PATA_INT 119
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
&isp1362_hcd_device,
#endif
};
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+static struct resource bfin_sir_resources[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ .start = 0xFFC00400,
+ .end = 0xFFC004FF,
+ .flags = IORESOURCE_MEM,
+ },
+#endif
+};
+
+static struct platform_device bfin_sir_device = {
+ .name = "bfin_sir",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bfin_sir_resources),
+ .resource = bfin_sir_resources,
+};
+#endif
+
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition ezkit_partitions[] = {
{
&bfin_uart_device,
#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+ &bfin_sir_device,
+#endif
+
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&bfin_pata_device,
#endif
+/*
+ * file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 2
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
--- /dev/null
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART0_RX,
+ CH_UART0_RX,
+ CH_UART0_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ 0xFFC02000,
+ IRQ_UART1_RX,
+ CH_UART1_RX,
+ CH_UART1_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR1
+ peripheral_request(P_UART1_TX, DRIVER_NAME);
+ peripheral_request(P_UART1_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
#define STATUS_P1 0x02
#define STATUS_P0 0x01
+#define BFIN_UART_NR_PORTS 2
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
+
/* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
+/*
+ * file: include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 1
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
#define DRIVER_NAME "bfin-uart"
-int nr_ports = NR_PORTS;
+int nr_ports = BFIN_UART_NR_PORTS;
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
--- /dev/null
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART_RX,
+ CH_UART_RX,
+ CH_UART_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
#include "cdefBF532.h"
#endif
+#define BFIN_UART_NR_PORTS 1
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
+
#endif /* _MACH_BLACKFIN_H_ */
+/*
+ * file: include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver header files
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 2
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
--- /dev/null
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART0_RX,
+ CH_UART0_RX,
+ CH_UART0_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ 0xFFC02000,
+ IRQ_UART1_RX,
+ CH_UART1_RX,
+ CH_UART1_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR1
+ peripheral_request(P_UART1_TX, DRIVER_NAME);
+ peripheral_request(P_UART1_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
#define BFIN_UART_GCTL UART0_GCTL
+#define BFIN_UART_NR_PORTS 2
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
+
/* DPMC*/
#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
+/*
+ * file: include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 4
-
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_GCTL 0x08 /* Global Control Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
-#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
-#define OFFSET_THR 0x28 /* Transmit Holding register */
-#define OFFSET_RBR 0x2C /* Receive Buffer register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#endif
};
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
--- /dev/null
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
+#define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART0_RX,
+ CH_UART0_RX,
+ CH_UART0_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR1
+ {
+ 0xFFC02000,
+ IRQ_UART1_RX,
+ CH_UART1_RX,
+ CH_UART1_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR2
+ {
+ 0xFFC02100,
+ IRQ_UART2_RX,
+ CH_UART2_RX,
+ CH_UART2_TX,
+ },
+#endif
+#ifdef CONFIG_BFIN_SIR3
+ {
+ 0xFFC03100,
+ IRQ_UART3_RX,
+ CH_UART3_RX,
+ CH_UART3_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR1
+ peripheral_request(P_UART1_TX, DRIVER_NAME);
+ peripheral_request(P_UART1_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR2
+ peripheral_request(P_UART2_TX, DRIVER_NAME);
+ peripheral_request(P_UART2_RX, DRIVER_NAME);
+#endif
+
+#ifdef CONFIG_BFIN_SIR3
+ peripheral_request(P_UART3_TX, DRIVER_NAME);
+ peripheral_request(P_UART3_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
#define BFIN_UART_SCR UART1_SCR
#define BFIN_UART_GCTL UART1_GCTL
+#define BFIN_UART_NR_PORTS 4
+
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_GCTL 0x08 /* Global Control Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
+#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
+#define OFFSET_THR 0x28 /* Transmit Holding register */
+#define OFFSET_RBR 0x2C /* Receive Buffer register */
+
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
+/*
+ * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
#include <asm/portmux.h>
-#define NR_PORTS 1
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
-
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
bfin_write16(uart->port.membase + OFFSET_LSR, -1);
}
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
#define DRIVER_NAME "bfin-uart"
-int nr_ports = NR_PORTS;
+int nr_ports = BFIN_UART_NR_PORTS;
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
--- /dev/null
+/*
+ * Blackfin Infra-red Driver
+ *
+ * Copyright 2006-2008 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ */
+
+#include <linux/serial.h>
+#include <asm/dma.h>
+#include <asm/portmux.h>
+
+#define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
+#define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
+#define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
+#define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
+#define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
+#define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
+#define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
+
+#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
+#define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
+#define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
+#define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
+#define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
+#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
+
+#ifdef CONFIG_SIR_BFIN_DMA
+struct dma_rx_buf {
+ char *buf;
+ int head;
+ int tail;
+ };
+#endif /* CONFIG_SIR_BFIN_DMA */
+
+struct bfin_sir_port {
+ unsigned char __iomem *membase;
+ unsigned int irq;
+ unsigned int lsr;
+ unsigned long clk;
+ struct net_device *dev;
+#ifdef CONFIG_SIR_BFIN_DMA
+ int tx_done;
+ struct dma_rx_buf rx_dma_buf;
+ struct timer_list rx_dma_timer;
+ int rx_dma_nrows;
+#endif /* CONFIG_SIR_BFIN_DMA */
+ unsigned int tx_dma_channel;
+ unsigned int rx_dma_channel;
+};
+
+struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
+
+struct bfin_sir_port_res {
+ unsigned long base_addr;
+ int irq;
+ unsigned int rx_dma_channel;
+ unsigned int tx_dma_channel;
+};
+
+struct bfin_sir_port_res bfin_sir_port_resource[] = {
+#ifdef CONFIG_BFIN_SIR0
+ {
+ 0xFFC00400,
+ IRQ_UART_RX,
+ CH_UART_RX,
+ CH_UART_TX,
+ },
+#endif
+};
+
+int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
+
+struct bfin_sir_self {
+ struct bfin_sir_port *sir_port;
+ spinlock_t lock;
+ unsigned int open;
+ int speed;
+ int newspeed;
+
+ struct sk_buff *txskb;
+ struct sk_buff *rxskb;
+ struct net_device_stats stats;
+ struct device *dev;
+ struct irlap_cb *irlap;
+ struct qos_info qos;
+
+ iobuff_t tx_buff;
+ iobuff_t rx_buff;
+
+ struct work_struct work;
+ int mtt;
+};
+
+static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
+{
+ unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
+ port->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | port->lsr;
+}
+
+static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
+{
+ port->lsr = 0;
+ bfin_read16(port->membase + OFFSET_LSR);
+}
+
+#define DRIVER_NAME "bfin_sir"
+
+static void bfin_sir_hw_init(void)
+{
+#ifdef CONFIG_BFIN_SIR0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+ SSYNC();
+}
#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
+#define BFIN_UART_NR_PORTS 1
+
+#define OFFSET_THR 0x00 /* Transmit Holding register */
+#define OFFSET_RBR 0x00 /* Receive Buffer register */
+#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
+#define OFFSET_IER 0x04 /* Interrupt Enable Register */
+#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
+#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
+#define OFFSET_LCR 0x0C /* Line Control Register */
+#define OFFSET_MCR 0x10 /* Modem Control Register */
+#define OFFSET_LSR 0x14 /* Line Status Register */
+#define OFFSET_MSR 0x18 /* Modem Status Register */
+#define OFFSET_SCR 0x1C /* SCR Scratch Register */
+#define OFFSET_GCTL 0x24 /* Global Control Register */
#endif /* _MACH_BLACKFIN_H_ */