Blackfin arch: workaround SIC_IWR1 reset bug, by keeping MDMA0/1 always enabled in...

This way we ensure that reboot succeeds.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 4271ef3f201a9d47b178652418dc459ee0c9c408..7f9df4ee7346bfcb1e55e3161be42a608a92e01c 100644 (file)
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1069,7 +1069,16 @@ int __init init_arch_irq(void)
 
 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
        bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
+#if defined(CONFIG_BF52x)
+       /* BF52x system reset does not properly reset SIC_IWR1 which
+        * will screw up the bootrom as it relies on MDMA0/1 waking it
+        * up from IDLE instructions.  See this report for more info:
+        * http://blackfin.uclinux.org/gf/tracker/4323
+        */
+       bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+#else
        bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
+#endif
 # ifdef CONFIG_BF54x
        bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif

diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index a17ace3e0e41fe38c5a4a6c2750188571db2d2d2..e28c6af1f4158e12b89bcecbee68363ede5d5745 100644 (file)
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -84,7 +84,16 @@ void bfin_pm_suspend_standby_enter(void)
 
 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)
        bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
+#if defined(CONFIG_BF52x)
+       /* BF52x system reset does not properly reset SIC_IWR1 which
+        * will screw up the bootrom as it relies on MDMA0/1 waking it
+        * up from IDLE instructions.  See this report for more info:
+        * http://blackfin.uclinux.org/gf/tracker/4323
+        */
+       bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
+#else
        bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
+#endif
 # ifdef CONFIG_BF54x
        bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif