[SPARC64]: Handle unimplemented FPU square-root on Niagara.

The math-emu code only expects unfinished fpop traps when
emulating FPU sqrt instructions on pre-Niagara chips.
On Niagara we can get unimplemented fpop, so handle that.

Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/arch/sparc64/math-emu/math.c b/arch/sparc64/math-emu/math.c
index 2ae05cd7b773fd2a45b3343968cd5ee072d5ea8e..a93a3664c85454e68e996c3e61b859bf62bd4a73 100644 (file)
--- a/arch/sparc64/math-emu/math.c
+++ b/arch/sparc64/math-emu/math.c
@@ -206,9 +206,30 @@ int do_mathemu(struct pt_regs *regs, struct fpustate *f)
                        case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
                        case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
                        case FQTOI: TYPE(3,1,0,3,1,0,0); break;
+
+                       /* We can get either unimplemented or unfinished
+                        * for these cases.  Pre-Niagara systems generate
+                        * unfinished fpop for SUBNORMAL cases, and Niagara
+                        * always gives unimplemented fpop for fsqrt{s,d}.
+                        */
+                       case FSQRTS: {
+                               unsigned long x = current_thread_info()->xfsr[0];
+
+                               x = (x >> 14) & 0xf;
+                               TYPE(x,1,1,1,1,0,0);
+                               printk("math-emu: type is %08x\n", type);
+                               break;
+                       }
+
+                       case FSQRTD: {
+                               unsigned long x = current_thread_info()->xfsr[0];
+
+                               x = (x >> 14) & 0xf;
+                               TYPE(x,2,1,2,1,0,0);
+                               break;
+                       }
+
                        /* SUBNORMAL - ftt == 2 */
-                       case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
-                       case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
                        case FADDD:
                        case FSUBD:
                        case FMULD: