#include <asm/io.h>
#define DRV_NAME "ehea"
-#define DRV_VERSION "EHEA_0089"
+#define DRV_VERSION "EHEA_0090"
/* eHEA capability flags */
#define DLPAR_PORT_ADD_REM 1
struct ehea_q_skb_arr rq2_skba;
struct ehea_q_skb_arr rq3_skba;
struct ehea_q_skb_arr sq_skba;
+ int sq_skba_size;
spinlock_t netif_queue;
int queue_stopped;
int swqe_refill_th;
pr->rq1_skba.os_skbs = 0;
if (unlikely(test_bit(__EHEA_STOP_XFER, &ehea_driver_flags))) {
- pr->rq1_skba.index = index;
+ if (nr_of_wqes > 0)
+ pr->rq1_skba.index = index;
pr->rq1_skba.os_skbs = fill_wqes;
return;
}
init_attr->act_nr_rwqes_rq2,
init_attr->act_nr_rwqes_rq3);
- ret = ehea_init_q_skba(&pr->sq_skba, init_attr->act_nr_send_wqes + 1);
+ pr->sq_skba_size = init_attr->act_nr_send_wqes + 1;
+
+ ret = ehea_init_q_skba(&pr->sq_skba, pr->sq_skba_size);
ret |= ehea_init_q_skba(&pr->rq1_skba, init_attr->act_nr_rwqes_rq1 + 1);
ret |= ehea_init_q_skba(&pr->rq2_skba, init_attr->act_nr_rwqes_rq2 + 1);
ret |= ehea_init_q_skba(&pr->rq3_skba, init_attr->act_nr_rwqes_rq3 + 1);
}
}
+void ehea_flush_sq(struct ehea_port *port)
+{
+ int i;
+
+ for (i = 0; i < port->num_def_qps + port->num_add_tx_qps; i++) {
+ struct ehea_port_res *pr = &port->port_res[i];
+ int swqe_max = pr->sq_skba_size - 2 - pr->swqe_ll_count;
+ int k = 0;
+ while (atomic_read(&pr->swqe_avail) < swqe_max) {
+ msleep(5);
+ if (++k == 20)
+ break;
+ }
+ }
+}
+
int ehea_stop_qps(struct net_device *dev)
{
struct ehea_port *port = netdev_priv(dev);
if (dev->flags & IFF_UP) {
down(&port->port_lock);
netif_stop_queue(dev);
+ ehea_flush_sq(port);
ret = ehea_stop_qps(dev);
if (ret) {
up(&port->port_lock);