imx serial: set RXD mux bit on i.MX27 and i.MX31

RX in i.MX27 and i.MX31 UART lines does not work unless the
"RXD  Muxed Input Select" bit is set on i.MX27 and i.MX31 processors.

This patch sets the missing RXD mux bit in the UCR3 register.

Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 20189c447e92abc954c5e54a34175c95f9d88721..312653e2f71508a62ee8a7df503237d3a7592421 100644 (file)
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -127,8 +127,13 @@
 #define  UCR3_RXDSEN    (1<<6)  /* Receive status interrupt enable */
 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 #define  UCR3_AWAKEN    (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25     (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30     (1<<2)  /* Ref Freq 30 MHz */
+#ifdef CONFIG_ARCH_IMX
+#define  UCR3_REF25     (1<<3)  /* Ref freq 25 MHz, only on mx1 */
+#define  UCR3_REF30     (1<<2)  /* Ref Freq 30 MHz, only on mx1 */
+#endif
+#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
+#define  UCR3_RXDMUXSEL         (1<<2)  /* RXD Muxed Input Select, on mx2/mx3 */
+#endif
 #define  UCR3_INVT      (1<<1)  /* Inverted Infrared transmission */
 #define  UCR3_BPEN      (1<<0)  /* Preset registers enable */
 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
@@ -598,6 +603,12 @@ static int imx_startup(struct uart_port *port)
        temp |= (UCR2_RXEN | UCR2_TXEN);
        writel(temp, sport->port.membase + UCR2);
 
+#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
+       temp = readl(sport->port.membase + UCR3);
+       temp |= UCR3_RXDMUXSEL;
+       writel(temp, sport->port.membase + UCR3);
+#endif
+
        /*
         * Enable modem status interrupts
         */