/* start peripherals off after the S3C2410 */
-#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x05000000))
+#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000))
-#define OSIRIS_PA_CPLD (S3C2410_CS1 | (3<<25))
+#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26))
/* we put the CPLD registers next, to get them out of the way */
-#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) /* 0x01300000 */
+#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000)
#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD)
-#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) /* 0x01400000 */
-#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<24))
+#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000)
+#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23))
-#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) /* 0x01500000 */
-#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<24))
+#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000)
+#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
-#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) /* 0x01600000 */
-#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<24))
+#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000)
+#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23))
#endif /* __ASM_ARCH_OSIRISMAP_H */