/* clock information */
static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
+
+DEFINE_MUTEX(clocks_mutex);
/* old functions */
.ctrlbit = 0,
};
+struct clk clk_usb_bus = {
+ .name = "usb-bus",
+ .id = -1,
+ .rate = 0,
+ .parent = &clk_upll,
+};
+
/* clocks that could be registered by external code */
static int s3c24xx_dclk_enable(struct clk *clk, int enable)
if (s3c24xx_register_clock(&clk_p) < 0)
printk(KERN_ERR "failed to register cpu pclk\n");
+
+ if (s3c24xx_register_clock(&clk_usb_bus) < 0)
+ printk(KERN_ERR "failed to register usb bus clock\n");
+
/* register clocks from clock array */
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
extern struct clk s3c24xx_clkout1;
extern struct clk s3c24xx_uclk;
+extern struct clk clk_usb_bus;
+
/* exports for arch/arm/mach-s3c2410
*
* Please DO NOT use these outside of arch/arm/mach-s3c2410
*/
+extern struct mutex clocks_mutex;
+
extern int s3c24xx_clkcon_enable(struct clk *clk, int enable);
extern int s3c24xx_register_clock(struct clk *clk);
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
+#include <linux/mutex.h>
#include <linux/clk.h>
#include <asm/hardware.h>
static int s3c2440_clk_add(struct sys_device *sysdev)
{
unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
+ unsigned long clkdivn;
struct clk *clk_h;
struct clk *clk_p;
+ struct clk *clk_upll;
printk("S3C2440: Clock Support, DVS %s\n",
(camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
clk_p = clk_get(NULL, "pclk");
clk_h = clk_get(NULL, "hclk");
+ clk_upll = clk_get(NULL, "upll");
- if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
+ if (IS_ERR(clk_p) || IS_ERR(clk_h) || IS_ERR(clk_upll)) {
printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
return -EINVAL;
}
+ /* check rate of UPLL, and if it is near 96MHz, then change
+ * to using half the UPLL rate for the system */
+
+ if (clk_get_rate(clk_upll) > (94 * MHZ)) {
+ clk_usb_bus.rate = clk_get_rate(clk_upll) / 2;
+
+ mutex_lock(&clocks_mutex);
+
+ clkdivn = __raw_readl(S3C2410_CLKDIVN);
+ clkdivn |= S3C2440_CLKDIVN_UCLK;
+ __raw_writel(camdivn, S3C2410_CLKDIVN);
+
+ mutex_unlock(&clocks_mutex);
+ }
+
s3c2440_clk_cam.parent = clk_h;
s3c2440_clk_ac97.parent = clk_p;
s3c2440_clk_cam_upll.parent = clk_upll;