[IA64] SGI Altix : fix pcibr_dmamap_ate32() bug

On a SGI Altix TIOCP based PCI bus we need to include the ATE_PIO attribute
bit if we're mapping a 32bit MSI address.

Signed-off-by: Mike Habeck <habeck@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index 1ee977fb6ebb8ab3d33fdf7cd184994b41856522..95af40cb22f216dd3dc160766bf46102e57d5273 100644 (file)
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -96,10 +96,14 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
        }
 
        /*
-        * If we're mapping for MSI, set the MSI bit in the ATE
+        * If we're mapping for MSI, set the MSI bit in the ATE.  If it's a
+        * TIOCP based pci bus, we also need to set the PIO bit in the ATE.
         */
-       if (dma_flags & SN_DMA_MSI)
+       if (dma_flags & SN_DMA_MSI) {
                ate |= PCI32_ATE_MSI;
+               if (IS_TIOCP_SOFT(pcibus_info))
+                       ate |= PCI32_ATE_PIO;
+       }
 
        ate_write(pcibus_info, ate_index, ate_count, ate);
 

diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index 17cb6cc3f21a8dc8899b55aaaa115436a2d2fa9a..da205b7cdaacf0ea77832bb957751ae17b6520e5 100644 (file)
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -21,6 +21,7 @@
 #define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
                 asic == PCIIO_ASIC_TYPE_TIOCP)
 #define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
+#define IS_TIOCP_SOFT(ps)   (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
 
 
 /*
@@ -53,8 +54,8 @@
  * Bridge PMU Address Transaltion Entry Attibutes
  */
 #define PCI32_ATE_V                     (0x1 << 0)
-#define PCI32_ATE_CO                    (0x1 << 1)
-#define PCI32_ATE_PREC                  (0x1 << 2)
+#define PCI32_ATE_CO                    (0x1 << 1)     /* PIC ASIC ONLY */
+#define PCI32_ATE_PIO                   (0x1 << 1)     /* TIOCP ASIC ONLY */
 #define PCI32_ATE_MSI                   (0x1 << 2)
 #define PCI32_ATE_PREF                  (0x1 << 3)
 #define PCI32_ATE_BAR                   (0x1 << 4)