saa7146_setgpio(saa, 3, SAA7146_GPIO_OUTLO);
/* Enable DEBI pins */
- saa7146_write(saa, MC1, saa7146_read(saa, MC1) | (0x800 << 16) | 0x800);
+ saa7146_write(saa, MC1, MASK_27 | MASK_11);
/* register CI interface */
budget_av->ca.owner = THIS_MODULE;
return 0;
error:
- saa7146_write(saa, MC1, saa7146_read(saa, MC1) | (0x800 << 16));
+ saa7146_write(saa, MC1, MASK_27);
return result;
}
dvb_ca_en50221_release(&budget_av->ca);
/* disable DEBI pins */
- saa7146_write(saa, MC1, saa7146_read(saa, MC1) | (0x800 << 16));
+ saa7146_write(saa, MC1, MASK_27);
}
memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221));
// enable DEBI pins
- saa7146_write(saa, MC1, saa7146_read(saa, MC1) | (0x800 << 16) | 0x800);
+ saa7146_write(saa, MC1, MASK_27 | MASK_11);
// test if it is there
ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0);
return 0;
error:
- saa7146_write(saa, MC1, saa7146_read(saa, MC1) | (0x800 << 16));
+ saa7146_write(saa, MC1, MASK_27);
return result;
}
dvb_ca_en50221_release(&budget_ci->ca);
// disable DEBI pins
- saa7146_write(saa, MC1, saa7146_read(saa, MC1) | (0x800 << 16));
+ saa7146_write(saa, MC1, MASK_27);
}
static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr)