NV_PORT0_SCR_REG_OFFSET = 0x00,
NV_PORT1_SCR_REG_OFFSET = 0x40,
+ /* INT_STATUS/ENABLE */
NV_INT_STATUS = 0x10,
- NV_INT_STATUS_CK804 = 0x440,
- NV_INT_STATUS_PDEV_INT = 0x01,
- NV_INT_STATUS_PDEV_PM = 0x02,
- NV_INT_STATUS_PDEV_ADDED = 0x04,
- NV_INT_STATUS_PDEV_REMOVED = 0x08,
- NV_INT_STATUS_SDEV_INT = 0x10,
- NV_INT_STATUS_SDEV_PM = 0x20,
- NV_INT_STATUS_SDEV_ADDED = 0x40,
- NV_INT_STATUS_SDEV_REMOVED = 0x80,
-
NV_INT_ENABLE = 0x11,
+ NV_INT_STATUS_CK804 = 0x440,
NV_INT_ENABLE_CK804 = 0x441,
- NV_INT_ENABLE_PDEV_MASK = 0x01,
- NV_INT_ENABLE_PDEV_PM = 0x02,
- NV_INT_ENABLE_PDEV_ADDED = 0x04,
- NV_INT_ENABLE_PDEV_REMOVED = 0x08,
- NV_INT_ENABLE_SDEV_MASK = 0x10,
- NV_INT_ENABLE_SDEV_PM = 0x20,
- NV_INT_ENABLE_SDEV_ADDED = 0x40,
- NV_INT_ENABLE_SDEV_REMOVED = 0x80,
+ /* INT_STATUS/ENABLE bits */
+ NV_INT_DEV = 0x01,
+ NV_INT_PM = 0x02,
+ NV_INT_ADDED = 0x04,
+ NV_INT_REMOVED = 0x08,
+
+ NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
+
+ /* INT_CONFIG */
NV_INT_CONFIG = 0x12,
NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
{
GENERIC,
NFORCE2,
- NFORCE3,
+ NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
CK804
};