[POWERPC] 86xx: Created quirk_fsl_pcie_transparent() to initialize bridge resources.

The Freescale PCI-e RC poses as a transparent bridge, but does not
implement the IO_BASE or IO_LIMIT registers in the config space.  This
means that the code which initializes the bridge resources ends up
setting the IO resources erroneously.  Add quick_fsl_pcie_transparent()
to handle this.

This change sets RC of mpc8641 to be a transparent bridge
for legacy I/O access and initializes the RC bridge resources
from the device tree.

Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index 6f3c0f674bbf2ed0090def363067d0a4dfb49559..2d7254c91ad9754faec3bc9d712257365120262b 100644 (file)
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -134,6 +134,43 @@ mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
        early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 }
 
+static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
+{
+       struct resource *res;
+       int i, res_idx = PCI_BRIDGE_RESOURCES;
+       struct pci_controller *hose;
+
+       /*
+        * Make the bridge be transparent.
+        */
+       dev->transparent = 1;
+
+       hose = pci_bus_to_hose(dev->bus->number);
+       if (!hose) {
+               printk(KERN_ERR "Can't find hose for bus %d\n",
+                      dev->bus->number);
+               return;
+       }
+
+       if (hose->io_resource.flags) {
+               res = &dev->resource[res_idx++];
+               res->start = hose->io_resource.start;
+               res->end = hose->io_resource.end;
+               res->flags = hose->io_resource.flags;
+       }
+
+       for (i = 0; i < 3; i++) {
+               res = &dev->resource[res_idx + i];
+               res->start = hose->mem_resources[i].start;
+               res->end = hose->mem_resources[i].end;
+               res->flags = hose->mem_resources[i].flags;
+       }
+}
+
+
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
+DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
+
 #define PCIE_LTSSM     0x404   /* PCIe Link Training and Status */
 #define PCIE_LTSSM_L0  0x16    /* L0 state */