[PATCH] Kill L1_CACHE_SHIFT_MAX

Kill L1_CACHE_SHIFT from all arches.  Since L1_CACHE_SHIFT_MAX is not used
anymore with the introduction of INTERNODE_CACHE, kill L1_CACHE_SHIFT_MAX.

Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org>
Signed-off-by: Shai Fultheim <shai@scalex86.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

diff --git a/include/asm-alpha/cache.h b/include/asm-alpha/cache.h
index e69b29501a5f2c5d477f6b375b6c0b6f69f9ea6e..e6d4d1695e256cdccce5a74d1b87edc8e99b8542 100644 (file)
--- a/include/asm-alpha/cache.h
+++ b/include/asm-alpha/cache.h
@@ -20,6 +20,5 @@
 
 #define L1_CACHE_ALIGN(x)  (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 #define SMP_CACHE_BYTES    L1_CACHE_BYTES
-#define L1_CACHE_SHIFT_MAX L1_CACHE_SHIFT
 
 #endif

diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
index 8d161f7c87ff7a059d26c119ece799f4675403dd..31332c8ac04ea0a21d184ff61db9044a094506a7 100644 (file)
--- a/include/asm-arm/cache.h
+++ b/include/asm-arm/cache.h
@@ -7,9 +7,4 @@
 #define L1_CACHE_SHIFT         5
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX     5
-
 #endif

diff --git a/include/asm-cris/arch-v10/cache.h b/include/asm-cris/arch-v10/cache.h
index 1d1d1ba65b1ae6c258b7b055b1b5ae5e686dc39a..aea27184d2d26645a14bda4e75e58bd2aeaaf7db 100644 (file)
--- a/include/asm-cris/arch-v10/cache.h
+++ b/include/asm-cris/arch-v10/cache.h
@@ -4,6 +4,5 @@
 /* Etrax 100LX have 32-byte cache-lines. */
 #define L1_CACHE_BYTES 32
 #define L1_CACHE_SHIFT 5
-#define L1_CACHE_SHIFT_MAX 5
 
 #endif /* _ASM_ARCH_CACHE_H */

diff --git a/include/asm-cris/arch-v32/cache.h b/include/asm-cris/arch-v32/cache.h
index 4fed8d62ccc88b251f67e1e101df0281370ef4a9..80b236b15319b6a1ea506949f429ceb332e6122d 100644 (file)
--- a/include/asm-cris/arch-v32/cache.h
+++ b/include/asm-cris/arch-v32/cache.h
@@ -4,6 +4,5 @@
 /* A cache-line is 32 bytes. */
 #define L1_CACHE_BYTES 32
 #define L1_CACHE_SHIFT 5
-#define L1_CACHE_SHIFT_MAX 5
 
 #endif /* _ASM_CRIS_ARCH_CACHE_H */

diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h
index 8eff51349ae75235f59764974031bf73f9705210..cbf1a98f012975d67ca8b3b5efd04b896ccc38b8 100644 (file)
--- a/include/asm-cris/dma-mapping.h
+++ b/include/asm-cris/dma-mapping.h
@@ -153,7 +153,7 @@ dma_set_mask(struct device *dev, u64 mask)
 static inline int
 dma_get_cache_alignment(void)
 {
-       return (1 << L1_CACHE_SHIFT_MAX);
+       return (1 << INTERNODE_CACHE_SHIFT);
 }
 
 #define dma_is_consistent(d)   (1)

diff --git a/include/asm-generic/dma-mapping.h b/include/asm-generic/dma-mapping.h
index 747d790295f3ddf02229f1a2838830f09ff22247..1b356207712c848a3e7318c96515d7fcac24608b 100644 (file)
--- a/include/asm-generic/dma-mapping.h
+++ b/include/asm-generic/dma-mapping.h
@@ -274,7 +274,7 @@ dma_get_cache_alignment(void)
 {
        /* no easy way to get cache size on all processors, so return
         * the maximum possible, to be safe */
-       return (1 << L1_CACHE_SHIFT_MAX);
+       return (1 << INTERNODE_CACHE_SHIFT);
 }
 
 static inline void

diff --git a/include/asm-i386/cache.h b/include/asm-i386/cache.h
index 849788710feb33fcecc22d695b8df92bbf44a06a..615911e5bd244e61a74ffe5d673054d6a7974a78 100644 (file)
--- a/include/asm-i386/cache.h
+++ b/include/asm-i386/cache.h
@@ -10,6 +10,4 @@
 #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
 
-#define L1_CACHE_SHIFT_MAX 7   /* largest L1 which this arch supports */
-
 #endif

diff --git a/include/asm-i386/dma-mapping.h b/include/asm-i386/dma-mapping.h
index e56c335f8ef9f0f5c7294eeee9e65a1b98d0165b..6c37a9ab8d607e5a7121fa227ee3785110a9ac7d 100644 (file)
--- a/include/asm-i386/dma-mapping.h
+++ b/include/asm-i386/dma-mapping.h
@@ -150,7 +150,7 @@ dma_get_cache_alignment(void)
 {
        /* no easy way to get cache size on all x86, so return the
         * maximum possible, to be safe */
-       return (1 << L1_CACHE_SHIFT_MAX);
+       return (1 << INTERNODE_CACHE_SHIFT);
 }
 
 #define dma_is_consistent(d)   (1)

diff --git a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
index 666d8f175cb3c99613667a21b91b2a100622d25d..40dd25195d656e0c171106a9735d931d7f0116e7 100644 (file)
--- a/include/asm-ia64/cache.h
+++ b/include/asm-ia64/cache.h
@@ -12,8 +12,6 @@
 #define L1_CACHE_SHIFT         CONFIG_IA64_L1_CACHE_SHIFT
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
-#define L1_CACHE_SHIFT_MAX 7   /* largest L1 which this arch supports */
-
 #ifdef CONFIG_SMP
 # define SMP_CACHE_SHIFT       L1_CACHE_SHIFT
 # define SMP_CACHE_BYTES       L1_CACHE_BYTES

diff --git a/include/asm-m32r/cache.h b/include/asm-m32r/cache.h
index 724820596980947f9c8d5a3baa7889a24271e23a..9c2b2d9998bc9e13397cb28cc9d21f91e3a42214 100644 (file)
--- a/include/asm-m32r/cache.h
+++ b/include/asm-m32r/cache.h
@@ -7,6 +7,4 @@
 #define L1_CACHE_SHIFT         4
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
-#define L1_CACHE_SHIFT_MAX     4
-
 #endif  /* _ASM_M32R_CACHE_H */

diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h
index 6161fd3d860040bb5babf9201b6e9f433d1a50d4..fed3fd30de7e468797a85ff5945119c436f92fce 100644 (file)
--- a/include/asm-m68k/cache.h
+++ b/include/asm-m68k/cache.h
@@ -8,6 +8,4 @@
 #define        L1_CACHE_SHIFT  4
 #define        L1_CACHE_BYTES  (1<< L1_CACHE_SHIFT)
 
-#define L1_CACHE_SHIFT_MAX 4   /* largest L1 which this arch supports */
-
 #endif

diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
index 1a5d1a669db382e4a2e398704b4052eddc083797..55e19f2ff0e012474a2d0f4c94a123e5e72bc9d9 100644 (file)
--- a/include/asm-mips/cache.h
+++ b/include/asm-mips/cache.h
@@ -15,7 +15,6 @@
 #define L1_CACHE_SHIFT         CONFIG_MIPS_L1_CACHE_SHIFT
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
-#define L1_CACHE_SHIFT_MAX     6
 #define SMP_CACHE_SHIFT                L1_CACHE_SHIFT
 #define SMP_CACHE_BYTES                L1_CACHE_BYTES
 

diff --git a/include/asm-parisc/cache.h b/include/asm-parisc/cache.h
index 5da72e38bdde4dd8a0599ac95e1f7d611319b233..38d201b5652dccd74e8ba4e1181e89be4ccba7c4 100644 (file)
--- a/include/asm-parisc/cache.h
+++ b/include/asm-parisc/cache.h
@@ -28,7 +28,6 @@
 #define L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 
 #define SMP_CACHE_BYTES L1_CACHE_BYTES
-#define L1_CACHE_SHIFT_MAX 5   /* largest L1 which this arch supports */
 
 extern void flush_data_cache_local(void);  /* flushes local data-cache only */
 extern void flush_instruction_cache_local(void); /* flushes local code-cache only */

diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
index 26ce502e76e82ace309a08a40b0da98d8edd7c65..6379c2df5c40ff51830e32ecbffd55a949bd0b7a 100644 (file)
--- a/include/asm-powerpc/cache.h
+++ b/include/asm-powerpc/cache.h
@@ -19,7 +19,6 @@
 #define        L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
 #define        SMP_CACHE_BYTES         L1_CACHE_BYTES
-#define L1_CACHE_SHIFT_MAX     7 /* largest L1 which this arch supports */
 
 #if defined(__powerpc64__) && !defined(__ASSEMBLY__)
 struct ppc64_caches {

diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index 59a80163f75fb2abac5dec482958012f784bef16..a96e5742ca324d302156b718766baa8ae1e9822c 100644 (file)
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -229,7 +229,7 @@ static inline int dma_get_cache_alignment(void)
 #ifdef CONFIG_PPC64
        /* no easy way to get cache size on all processors, so return
         * the maximum possible, to be safe */
-       return (1 << L1_CACHE_SHIFT_MAX);
+       return (1 << INTERNODE_CACHE_SHIFT);
 #else
        /*
         * Each processor family will define its own L1_CACHE_SHIFT,

diff --git a/include/asm-s390/cache.h b/include/asm-s390/cache.h
index 29845378b206d428b55a92f01c4d2afc69cc4a56..e20cdd9074db398cc5d7440600fa22e3d8cb66ee 100644 (file)
--- a/include/asm-s390/cache.h
+++ b/include/asm-s390/cache.h
@@ -13,7 +13,6 @@
 
 #define L1_CACHE_BYTES     256
 #define L1_CACHE_SHIFT     8
-#define L1_CACHE_SHIFT_MAX 8   /* largest L1 which this arch supports */
 
 #define ARCH_KMALLOC_MINALIGN  8
 

diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h
index 9b4dd6d8212ea0fcc48f32836c4a2f654140927d..656fdfe9e8b445ee16e6f833e62f7e10bc783a20 100644 (file)
--- a/include/asm-sh/cache.h
+++ b/include/asm-sh/cache.h
@@ -22,8 +22,6 @@
 
 #define L1_CACHE_ALIGN(x)      (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 
-#define L1_CACHE_SHIFT_MAX     5       /* largest L1 which this arch supports */
-
 struct cache_info {
        unsigned int ways;
        unsigned int sets;

diff --git a/include/asm-sh64/cache.h b/include/asm-sh64/cache.h
index f54e85e8a47028a2e401b75ecad50e85e69d420a..a4f36f0036e1fd7f1f9e689a9faa38a690a5ea61 100644 (file)
--- a/include/asm-sh64/cache.h
+++ b/include/asm-sh64/cache.h
@@ -20,8 +20,6 @@
 #define L1_CACHE_ALIGN_MASK    (~(L1_CACHE_BYTES - 1))
 #define L1_CACHE_ALIGN(x)      (((x)+(L1_CACHE_BYTES - 1)) & L1_CACHE_ALIGN_MASK)
 #define L1_CACHE_SIZE_BYTES    (L1_CACHE_BYTES << 10)
-/* Largest L1 which this arch supports */
-#define L1_CACHE_SHIFT_MAX     5
 
 #ifdef MODULE
 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))

diff --git a/include/asm-sparc/cache.h b/include/asm-sparc/cache.h
index a10522cb21b7d311b698f48b7a751b216a10dad6..cb971e88aea4f7b3a355a1b2505df188d432fec2 100644 (file)
--- a/include/asm-sparc/cache.h
+++ b/include/asm-sparc/cache.h
@@ -13,7 +13,6 @@
 #define L1_CACHE_SHIFT 5
 #define L1_CACHE_BYTES 32
 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
-#define L1_CACHE_SHIFT_MAX 5   /* largest L1 which this arch supports */
 
 #define SMP_CACHE_BYTES 32
 

diff --git a/include/asm-sparc64/cache.h b/include/asm-sparc64/cache.h
index ade5ec3bfd5a23ca18e08acc4185ed3d908589b1..f7d35a2ae9b8a41401b73f70b74080080ddfcba4 100644 (file)
--- a/include/asm-sparc64/cache.h
+++ b/include/asm-sparc64/cache.h
@@ -9,7 +9,6 @@
 #define        L1_CACHE_BYTES  32 /* Two 16-byte sub-blocks per line. */
 
 #define        L1_CACHE_ALIGN(x)       (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
-#define                L1_CACHE_SHIFT_MAX 5    /* largest L1 which this arch supports */
 
 #define        SMP_CACHE_BYTES_SHIFT   6
 #define        SMP_CACHE_BYTES         (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */

diff --git a/include/asm-um/cache.h b/include/asm-um/cache.h
index a10602a5b2d6395ef697dbe7381278d4997ecf8f..3d0587075521ee3fb3108dfdcf3c219cb5467125 100644 (file)
--- a/include/asm-um/cache.h
+++ b/include/asm-um/cache.h
@@ -13,9 +13,6 @@
 # define L1_CACHE_SHIFT                5
 #endif
 
-/* XXX: this is valid for x86 and x86_64. */
-#define L1_CACHE_SHIFT_MAX     7       /* largest L1 which this arch supports */
-
 #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
 
 #endif

diff --git a/include/asm-v850/cache.h b/include/asm-v850/cache.h
index cbf9096e8517bb3a9698c1284e177210cbee5654..8832c7ea3242b08bf99993fe67f47a06fe8d9b70 100644 (file)
--- a/include/asm-v850/cache.h
+++ b/include/asm-v850/cache.h
@@ -23,6 +23,4 @@
 #define L1_CACHE_SHIFT         4
 #endif
 
-#define L1_CACHE_SHIFT_MAX     L1_CACHE_SHIFT
-
 #endif /* __V850_CACHE_H__ */

diff --git a/include/asm-x86_64/cache.h b/include/asm-x86_64/cache.h
index 33e53424128b33a4096162bfe29848b2885a8b16..b4a2401de77b5824239f1ec8b38d9b578d839e68 100644 (file)
--- a/include/asm-x86_64/cache.h
+++ b/include/asm-x86_64/cache.h
@@ -9,6 +9,5 @@
 /* L1 cache line size */
 #define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#define L1_CACHE_SHIFT_MAX 7   /* largest L1 which this arch supports */
 
 #endif