[ARM] 3036/1: AAEC-2000 - Add defines for GPIO registers

Patch from Bellido Nicolas

Add defines for GPIO registers on the AAEC-2000 processor.

Signed-off-by: Nicolas Bellido <ml@acolin.be>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
index 0e9b7e18af05650cd80aca9eec46b4791ed8a686..7472f9e5523f19da6bc0ae791efd1e3fd65e1a10 100644 (file)
--- a/include/asm-arm/arch-aaec2000/aaec2000.h
+++ b/include/asm-arm/arch-aaec2000/aaec2000.h
@@ -17,6 +17,13 @@
 #error You must include hardware.h not this file
 #endif /* __ASM_ARCH_HARDWARE_H */
 
+/* Chip selects */
+#define AAEC_CS0       0x00000000
+#define AAEC_CS1       0x10000000
+#define AAEC_CS2       0x20000000
+#define AAEC_CS3       0x30000000
+
+
 /* Interrupt controller */
 #define IRQ_BASE       __REG(0x80000500)
 #define IRQ_INTSR      __REG(0x80000500)       /* Int Status Register */
@@ -148,4 +155,47 @@
 #define POWER_STFCLR   __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
 #define POWER_CLKSET   __REG(0x80000420) /* Clock Speed Control */
 
+/* GPIO Registers */
+#define AAEC_GPIO_PHYS 0x80000e00
+
+#define AAEC_GPIO_PADR         __REG(AAEC_GPIO_PHYS + 0x00)
+#define AAEC_GPIO_PBDR         __REG(AAEC_GPIO_PHYS + 0x04)
+#define AAEC_GPIO_PCDR         __REG(AAEC_GPIO_PHYS + 0x08)
+#define AAEC_GPIO_PDDR         __REG(AAEC_GPIO_PHYS + 0x0c)
+#define AAEC_GPIO_PADDR                __REG(AAEC_GPIO_PHYS + 0x10)
+#define AAEC_GPIO_PBDDR                __REG(AAEC_GPIO_PHYS + 0x14)
+#define AAEC_GPIO_PCDDR                __REG(AAEC_GPIO_PHYS + 0x18)
+#define AAEC_GPIO_PDDDR                __REG(AAEC_GPIO_PHYS + 0x1c)
+#define AAEC_GPIO_PEDR         __REG(AAEC_GPIO_PHYS + 0x20)
+#define AAEC_GPIO_PEDDR                __REG(AAEC_GPIO_PHYS + 0x24)
+#define AAEC_GPIO_KSCAN                __REG(AAEC_GPIO_PHYS + 0x28)
+#define AAEC_GPIO_PINMUX       __REG(AAEC_GPIO_PHYS + 0x2c)
+#define AAEC_GPIO_PFDR         __REG(AAEC_GPIO_PHYS + 0x30)
+#define AAEC_GPIO_PFDDR                __REG(AAEC_GPIO_PHYS + 0x34)
+#define AAEC_GPIO_PGDR         __REG(AAEC_GPIO_PHYS + 0x38)
+#define AAEC_GPIO_PGDDR                __REG(AAEC_GPIO_PHYS + 0x3c)
+#define AAEC_GPIO_PHDR         __REG(AAEC_GPIO_PHYS + 0x40)
+#define AAEC_GPIO_PHDDR                __REG(AAEC_GPIO_PHYS + 0x44)
+#define AAEC_GPIO_RAZ          __REG(AAEC_GPIO_PHYS + 0x48)
+#define AAEC_GPIO_INTTYPE1     __REG(AAEC_GPIO_PHYS + 0x4c)
+#define AAEC_GPIO_INTTYPE2     __REG(AAEC_GPIO_PHYS + 0x50)
+#define AAEC_GPIO_FEOI         __REG(AAEC_GPIO_PHYS + 0x54)
+#define AAEC_GPIO_INTEN                __REG(AAEC_GPIO_PHYS + 0x58)
+#define AAEC_GPIO_INTSTATUS    __REG(AAEC_GPIO_PHYS + 0x5c)
+#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
+#define AAEC_GPIO_DB           __REG(AAEC_GPIO_PHYS + 0x64)
+#define AAEC_GPIO_PAPINDR      __REG(AAEC_GPIO_PHYS + 0x68)
+#define AAEC_GPIO_PBPINDR      __REG(AAEC_GPIO_PHYS + 0x6c)
+#define AAEC_GPIO_PCPINDR      __REG(AAEC_GPIO_PHYS + 0x70)
+#define AAEC_GPIO_PDPINDR      __REG(AAEC_GPIO_PHYS + 0x74)
+#define AAEC_GPIO_PEPINDR      __REG(AAEC_GPIO_PHYS + 0x78)
+#define AAEC_GPIO_PFPINDR      __REG(AAEC_GPIO_PHYS + 0x7c)
+#define AAEC_GPIO_PGPINDR      __REG(AAEC_GPIO_PHYS + 0x80)
+#define AAEC_GPIO_PHPINDR      __REG(AAEC_GPIO_PHYS + 0x84)
+
+#define AAEC_GPIO_PINMUX_PE0CON                (1 << 0)
+#define AAEC_GPIO_PINMUX_PD0CON                (1 << 1)
+#define AAEC_GPIO_PINMUX_CODECON       (1 << 2)
+#define AAEC_GPIO_PINMUX_UART3CON      (1 << 3)
+
 #endif /* __ARM_ARCH_AAEC2000_H */