ha = dev_id;
reg = &ha->iobase->isp24;
- spin_lock(&ha->hardware_lock);
+ spin_lock_irq(&ha->hardware_lock);
qla24xx_process_response_queue(ha);
WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
- spin_unlock(&ha->hardware_lock);
+ spin_unlock_irq(&ha->hardware_lock);
return IRQ_HANDLED;
}
reg = &ha->iobase->isp24;
status = 0;
- spin_lock(&ha->hardware_lock);
+ spin_lock_irq(&ha->hardware_lock);
do {
stat = RD_REG_DWORD(®->host_status);
if (stat & HSRX_RISC_PAUSED) {
}
WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
} while (0);
- spin_unlock(&ha->hardware_lock);
+ spin_unlock_irq(&ha->hardware_lock);
if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
(status & MBX_INTERRUPT) && ha->flags.mbox_int) {