tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
break;
}
+ if (state->config->ts_mode == 0) {
+ tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
+ tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
+ } else {
+ tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
+ tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
+ state->config->invert_oclk << 4);
+ }
tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
- tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x79); // Turn IF AGC output on
+ tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
// tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
- tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
return 0;
}
TDA10046_FREQ_052, /* low IF, 5.1667 MHZ for tda9889 */
};
+enum tda10046_tsout {
+ TDA10046_TS_PARALLEL = 0x00, /* parallel transport stream, default */
+ TDA10046_TS_SERIAL = 0x01, /* serial transport stream */
+};
+
struct tda1004x_config
{
/* the demodulator's i2c address */
/* Does the OCLK signal need inverted? */
u8 invert_oclk;
+ /* parallel or serial transport stream */
+ enum tda10046_tsout ts_mode;
+
/* Xtal frequency, 4 or 16MHz*/
enum tda10046_xtal xtal_freq;