]> err.no Git - linux-2.6/commitdiff
[MIPS] TXx9: Add some pci options
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Wed, 23 Jul 2008 15:25:15 +0000 (00:25 +0900)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 30 Jul 2008 20:54:38 +0000 (21:54 +0100)
Add pci options for backplane type, clock selection, error handling,
timeout values.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pci/ops-tx4927.c
arch/mips/txx9/generic/pci.c
arch/mips/txx9/generic/setup.c
arch/mips/txx9/rbtx4927/setup.c
arch/mips/txx9/rbtx4938/setup.c
include/asm-mips/txx9/pci.h
include/asm-mips/txx9/tx4927pcic.h

index 6d844094ef5d6de50786d99e7f8f35679fe17d6b..038e311b069d29e3f48ae64e5d9ff23948591051 100644 (file)
@@ -194,6 +194,28 @@ static struct {
        .gbwc = 0xfe0,  /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
 };
 
+char *__devinit tx4927_pcibios_setup(char *str)
+{
+       unsigned long val;
+
+       if (!strncmp(str, "trdyto=", 7)) {
+               if (strict_strtoul(str + 7, 0, &val) == 0)
+                       tx4927_pci_opts.trdyto = val;
+               return NULL;
+       }
+       if (!strncmp(str, "retryto=", 8)) {
+               if (strict_strtoul(str + 8, 0, &val) == 0)
+                       tx4927_pci_opts.retryto = val;
+               return NULL;
+       }
+       if (!strncmp(str, "gbwc=", 5)) {
+               if (strict_strtoul(str + 5, 0, &val) == 0)
+                       tx4927_pci_opts.gbwc = val;
+               return NULL;
+       }
+       return str;
+}
+
 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
                              struct pci_controller *channel, int extarb)
 {
index 0b92d8c13208a085309538f5b97cf228baddc3c6..7b637a7c0e6694d7bbae5c3ec895093fb2f6491e 100644 (file)
@@ -386,3 +386,39 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        return txx9_board_vec->pci_map_irq(dev, slot, pin);
 }
+
+char * (*txx9_board_pcibios_setup)(char *str) __devinitdata;
+
+char *__devinit txx9_pcibios_setup(char *str)
+{
+       if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
+               return NULL;
+       if (!strcmp(str, "picmg")) {
+               /* PICMG compliant backplane (TOSHIBA JMB-PICMG-ATX
+                  (5V or 3.3V), JMB-PICMG-L2 (5V only), etc.) */
+               txx9_pci_option |= TXX9_PCI_OPT_PICMG;
+               return NULL;
+       } else if (!strcmp(str, "nopicmg")) {
+               /* non-PICMG compliant backplane (TOSHIBA
+                  RBHBK4100,RBHBK4200, Interface PCM-PCM05, etc.) */
+               txx9_pci_option &= ~TXX9_PCI_OPT_PICMG;
+               return NULL;
+       } else if (!strncmp(str, "clk=", 4)) {
+               char *val = str + 4;
+               txx9_pci_option &= ~TXX9_PCI_OPT_CLK_MASK;
+               if (strcmp(val, "33") == 0)
+                       txx9_pci_option |= TXX9_PCI_OPT_CLK_33;
+               else if (strcmp(val, "66") == 0)
+                       txx9_pci_option |= TXX9_PCI_OPT_CLK_66;
+               else /* "auto" */
+                       txx9_pci_option |= TXX9_PCI_OPT_CLK_AUTO;
+               return NULL;
+       } else if (!strncmp(str, "err=", 4)) {
+               if (!strcmp(str + 4, "panic"))
+                       txx9_pci_err_action = TXX9_PCI_ERR_PANIC;
+               else if (!strcmp(str + 4, "ignore"))
+                       txx9_pci_err_action = TXX9_PCI_ERR_IGNORE;
+               return NULL;
+       }
+       return str;
+}
index 8c60c78b9a9e0506d2eb3307e6bbda8e1dbef710..4fbd7baa7037284b442eb5dad961fb94e4ccf5f0 100644 (file)
@@ -23,6 +23,7 @@
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 #include <asm/txx9/generic.h>
+#include <asm/txx9/pci.h>
 #ifdef CONFIG_CPU_TX49XX
 #include <asm/txx9/tx4938.h>
 #endif
@@ -194,6 +195,9 @@ void __init plat_mem_setup(void)
        ioport_resource.end = ~0UL;     /* no limit */
        iomem_resource.start = 0;
        iomem_resource.end = ~0UL;      /* no limit */
+#ifdef CONFIG_PCI
+       pcibios_plat_setup = txx9_pcibios_setup;
+#endif
        txx9_board_vec->mem_setup();
 }
 
index 3da20ea3e55ceb36259580408115ee05d763bf0e..88c05ccee3b2e66c634deb06b644438f7cd6a084 100644 (file)
@@ -238,6 +238,7 @@ static void __init rbtx4927_mem_setup(void)
        txx9_alloc_pci_controller(&txx9_primary_pcic,
                                  RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
                                  RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
+       txx9_board_pcibios_setup = tx4927_pcibios_setup;
 #else
        set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
 #endif
index 6c2b99bb8af630e1d9c1b176ebd5b927689b11da..fc9034db526e8eb58495ec842b789e3d1d00aa2b 100644 (file)
@@ -193,6 +193,7 @@ static void __init rbtx4938_mem_setup(void)
 
 #ifdef CONFIG_PCI
        txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
+       txx9_board_pcibios_setup = tx4927_pcibios_setup;
 #else
        set_io_port_base(RBTX4938_ETHER_BASE);
 #endif
index d89a45091e2403cd8aeec2197248a31c5fcf21f3..3d32529060aaf999090253b3b86b117364e5204b 100644 (file)
@@ -33,4 +33,7 @@ enum txx9_pci_err_action {
 };
 extern enum txx9_pci_err_action txx9_pci_err_action;
 
+extern char * (*txx9_board_pcibios_setup)(char *str);
+char *txx9_pcibios_setup(char *str);
+
 #endif /* __ASM_TXX9_PCI_H */
index d61c3d09c4a222ce584ec053dcde3b9d8a7828aa..e1d78e9ebc064c737a34eeedb663b9eaf04b1632 100644 (file)
@@ -195,5 +195,6 @@ struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
 void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
                              struct pci_controller *channel, int extarb);
 void tx4927_report_pcic_status(void);
+char *tx4927_pcibios_setup(char *str);
 
 #endif /* __ASM_TXX9_TX4927PCIC_H */