struct iwl4965_shared {
struct iwl4965_sched_queue_byte_cnt_tbl
queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];
- __le32 val0;
+ __le32 rb_closed;
/* __le32 rb_closed_stts_rb_num:12; */
#define IWL_rb_closed_stts_rb_num_POS 0
#define IWL_rb_closed_stts_rb_num_LEN 12
-#define IWL_rb_closed_stts_rb_num_SYM val0
+#define IWL_rb_closed_stts_rb_num_SYM rb_closed
/* __le32 rsrv1:4; */
/* __le32 rb_closed_stts_rx_frame_num:12; */
#define IWL_rb_closed_stts_rx_frame_num_POS 16
#define IWL_rb_closed_stts_rx_frame_num_LEN 12
-#define IWL_rb_closed_stts_rx_frame_num_SYM val0
+#define IWL_rb_closed_stts_rx_frame_num_SYM rb_closed
/* __le32 rsrv2:4; */
- __le32 val1;
+ __le32 frm_finished;
/* __le32 frame_finished_stts_rb_num:12; */
#define IWL_frame_finished_stts_rb_num_POS 0
#define IWL_frame_finished_stts_rb_num_LEN 12
-#define IWL_frame_finished_stts_rb_num_SYM val1
+#define IWL_frame_finished_stts_rb_num_SYM frm_finished
/* __le32 rsrv3:4; */
/* __le32 frame_finished_stts_rx_frame_num:12; */
#define IWL_frame_finished_stts_rx_frame_num_POS 16
#define IWL_frame_finished_stts_rx_frame_num_LEN 12
-#define IWL_frame_finished_stts_rx_frame_num_SYM val1
+#define IWL_frame_finished_stts_rx_frame_num_SYM frm_finished
/* __le32 rsrv4:4; */
__le32 padding1; /* so that allocation will be aligned to 16B */
spin_lock_init(&priv->hcmd_lock);
spin_lock_init(&priv->lq_mngr.lock);
+ priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
+ sizeof(struct iwl4965_shared),
+ &priv->shared_phys);
+
+ if (!priv->shared_virt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
+
+
for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
{
- int rc;
+ int ret;
unsigned long flags;
unsigned int rb_size;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_nic_access(priv);
- if (rc) {
+ ret = iwl_grab_nic_access(priv);
+ if (ret) {
spin_unlock_irqrestore(&priv->lock, flags);
- return rc;
+ return ret;
}
if (priv->cfg->mod_params->amsdu_size_8K)
/* Tell device where in DRAM to update its Rx status */
iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
- (priv->hw_setting.shared_phys +
- offsetof(struct iwl4965_shared, val0)) >> 4);
+ (priv->shared_phys +
+ offsetof(struct iwl4965_shared, rb_closed)) >> 4);
/* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
rb_size |
- /*0x10 << 4 | */
+ /* 0x10 << 4 | */
(RX_QUEUE_SIZE_LOG <<
FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
/* Tel 4965 where to find Tx byte count tables */
iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
- (priv->hw_setting.shared_phys +
+ (priv->shared_phys +
offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
/* Disable chain mode for all queues */
*/
int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
{
- int ret = 0;
if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
(priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
IWL_ERROR("invalid queues_num, should be between %d and %d\n",
IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
- ret = -EINVAL;
- goto out;
- }
-
- /* Allocate area for Tx byte count tables and Rx queue status */
- priv->hw_setting.shared_virt =
- pci_alloc_consistent(priv->pci_dev,
- sizeof(struct iwl4965_shared),
- &priv->hw_setting.shared_phys);
-
- if (!priv->hw_setting.shared_virt) {
- ret = -ENOMEM;
- goto out;
+ return -EINVAL;
}
- memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
-
priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
priv->hw_setting.tx_ant_num = 2;
-out:
- return ret;
+ return 0;
}
/**
int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
{
- struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
-
- return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
+ struct iwl4965_shared *s = priv->shared_virt;
+ return le32_to_cpu(s->rb_closed) & 0xFFF;
}
int iwl4965_hw_get_temperature(struct iwl_priv *priv)
{
int len;
int txq_id = txq->q.id;
- struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
+ struct iwl4965_shared *shared_data = priv->shared_virt;
len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
* @max_rxq_log: Log-base-2 of max_rxq_size
* @max_stations:
* @bcast_sta_id:
- * @shared_virt: Pointer to driver/uCode shared Tx Byte Counts and Rx status
- * @shared_phys: Physical Pointer to Tx Byte Counts and Rx status
*/
struct iwl4965_driver_hw_info {
u16 max_txq_num;
u16 max_rxq_log;
u8 max_stations;
u8 bcast_sta_id;
- void *shared_virt;
- dma_addr_t shared_phys;
};
#define HT_SHORT_GI_20MHZ_ONLY (1 << 0)
/* Last Rx'd beacon timestamp */
u64 timestamp;
u16 beacon_int;
- struct iwl4965_driver_hw_info hw_setting;
struct ieee80211_vif *vif;
+ struct iwl4965_driver_hw_info hw_setting;
+ /* driver/uCode shared Tx Byte Counts and Rx status */
+ void *shared_virt;
+ /* Physical Pointer to Tx Byte Counts and Rx status */
+ dma_addr_t shared_phys;
+
/* Current association information needed to configure the
* hardware */
u16 assoc_id;