+ if ( (ts1_status & VID_B_MSK_OPC_ERR) ||
+ (ts1_status & VID_B_MSK_BAD_PKT) ||
+ (ts1_status & VID_B_MSK_SYNC) ||
+ (ts1_status & VID_B_MSK_OF))
+ {
+ if (ts1_status & VID_B_MSK_OPC_ERR)
+ dprintk(7, " (VID_B_MSK_OPC_ERR 0x%08x)\n", VID_B_MSK_OPC_ERR);
+ if (ts1_status & VID_B_MSK_BAD_PKT)
+ dprintk(7, " (VID_B_MSK_BAD_PKT 0x%08x)\n", VID_B_MSK_BAD_PKT);
+ if (ts1_status & VID_B_MSK_SYNC)
+ dprintk(7, " (VID_B_MSK_SYNC 0x%08x)\n", VID_B_MSK_SYNC);
+ if (ts1_status & VID_B_MSK_OF)
+ dprintk(7, " (VID_B_MSK_OF 0x%08x)\n", VID_B_MSK_OF);
+
+ printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
+
+ cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
+ cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
+
+ } else if (ts1_status & VID_B_MSK_RISCI1) {
+
+ dprintk(7, " (RISCI1 0x%08x)\n", VID_B_MSK_RISCI1);
+
+ spin_lock(&port->slock);
+ count = cx_read(port->reg_gpcnt);
+ cx23885_wakeup(port, &port->mpegq, count);
+ spin_unlock(&port->slock);
+
+ } else if (ts1_status & VID_B_MSK_RISCI2) {
+
+ dprintk(7, " (RISCI2 0x%08x)\n", VID_B_MSK_RISCI2);
+
+ spin_lock(&port->slock);
+ cx23885_restart_queue(port, &port->mpegq);
+ spin_unlock(&port->slock);
+
+ }
+ if (ts1_status) {
+ cx_write(VID_B_INT_STAT, ts1_status);
+ handled = 1;
+ }
+