[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.

[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.

Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>