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[ARM] Feroceon: L1 cache range operation support
authorStanislav Samsonov <samsonov@marvell.com>
Tue, 3 Jun 2008 08:24:40 +0000 (11:24 +0300)
committerLennert Buytenhek <buytenh@marvell.com>
Sun, 22 Jun 2008 20:45:03 +0000 (22:45 +0200)
commit836a8051d54525e0782f156dcfa3c13d30f22840
treea72c16e6bbfb4b4768562bc9757bdd04b17e4c7ftree | snapshot
parent7ea217a85e38c5ed6edbc789670badb619da9f28commit | diff
[ARM] Feroceon: L1 cache range operation support

This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
arch/arm/mm/proc-feroceon.S diff | blob | history
include/asm-arm/cacheflush.h diff | blob | history
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