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[IA64] Update Altix nofault code
authorRuss Anderson <rja@sgi.com>
Thu, 3 Jan 2008 16:23:49 +0000 (10:23 -0600)
committerTony Luck <tony.luck@intel.com>
Thu, 3 Jan 2008 21:22:54 +0000 (13:22 -0800)
commit2022c1f136067f673964dcaffa1cae1008ddcd74
treee62db392a3d730156fe8ca62d9e7d507f3e1a8detree | snapshot
parent4ca8ad7e4c38cd7f32b11e60418d06fa912a1a37commit | diff
[IA64] Update Altix nofault code

Montecito and Montvale behaves slightly differently than previous
Itanium processors, resulting in the MCA due to a failed PIO read
to sometimes surfacing outside the nofault code.  This code is
based on discussions with Intel CPU architects and verified at
customer sites.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
arch/ia64/sn/kernel/xp_nofault.S diff | blob | history
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