X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=include%2Flinux%2Fmtd%2Fnand.h;h=8b3ef418721980542adccfb4feb8cc63f82410af;hb=351edd240d0ba8620789ca9e24f5a38b62157f23;hp=a30969eb9afe694d2a2a62c554b8c5f473f41c6a;hpb=2edc322d420a4cec8dbc184a1220ecd7fa9f8ae6;p=linux-2.6 diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index a30969eb9a..8b3ef41872 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -20,7 +20,6 @@ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H -#include #include #include #include @@ -28,9 +27,17 @@ struct mtd_info; /* Scan and identify a NAND device */ extern int nand_scan (struct mtd_info *mtd, int max_chips); +/* Separate phases of nand_scan(), allowing board driver to intervene + * and override command or ECC setup according to flash type */ +extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); +extern int nand_scan_tail(struct mtd_info *mtd); + /* Free resources held by the NAND device */ extern void nand_release (struct mtd_info *mtd); +/* Internal helper for board drivers which need to override command function */ +extern void nand_wait_ready(struct mtd_info *mtd); + /* The maximum number of NAND chips in an array */ #define NAND_MAX_CHIPS 8 @@ -179,7 +186,9 @@ typedef enum { #define NAND_USE_FLASH_BBT 0x00010000 /* This option skips the bbt scan during initialization. */ #define NAND_SKIP_BBTSCAN 0x00020000 - +/* This option is defined if the board driver allocates its own buffers + (e.g. because it needs them DMA-coherent */ +#define NAND_OWN_BUFFERS 0x00040000 /* Options set by nand scan */ /* Nand scan has allocated controller struct */ #define NAND_CONTROLLER_ALLOC 0x80000000 @@ -203,7 +212,7 @@ typedef enum { struct nand_chip; /** - * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices + * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices * @lock: protection lock * @active: the mtd device which holds the controller currently * @wq: wait queue to sleep on if a NAND operation is in progress @@ -224,12 +233,17 @@ struct nand_hw_control { * @total: total number of ecc bytes per page * @prepad: padding information for syndrome based ecc generators * @postpad: padding information for syndrome based ecc generators + * @layout: ECC layout control struct pointer * @hwctl: function to control hardware ecc generator. Must only * be provided if an hardware ECC is available * @calculate: function for ecc calculation or readback from ecc hardware * @correct: function for ecc correction, matching to ecc generator (sw/hw) + * @read_page_raw: function to read a raw page without ECC + * @write_page_raw: function to write a raw page without ECC * @read_page: function to read a page according to the ecc generator requirements * @write_page: function to write a page according to the ecc generator requirements + * @read_oob: function to read chip OOB data + * @write_oob: function to write chip OOB data */ struct nand_ecc_ctrl { nand_ecc_modes_t mode; @@ -247,6 +261,12 @@ struct nand_ecc_ctrl { int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc); + int (*read_page_raw)(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf); + void (*write_page_raw)(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf); int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf); @@ -301,11 +321,15 @@ struct nand_buffers { * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready * @ecc: [BOARDSPECIFIC] ecc control ctructure + * @buffers: buffer structure for read/write + * @hwcontrol: platform-specific hardware control structure + * @ops: oob operation operands * @erase_cmd: [INTERN] erase command write function, selectable due to AND support * @scan_bbt: [REPLACEABLE] function to scan bad block table * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress * @state: [INTERN] the current state of the NAND device + * @oob_poi: poison value buffer * @page_shift: [INTERN] number of address bits in a page (column address bits) * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry @@ -331,6 +355,7 @@ struct nand_buffers { * @priv: [OPTIONAL] pointer to private chip date * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks * (determine if errors are correctable) + * @write_page: [REPLACEABLE] High-level page write function */ struct nand_chip { @@ -353,6 +378,8 @@ struct nand_chip { void (*erase_cmd)(struct mtd_info *mtd, int page); int (*scan_bbt)(struct mtd_info *mtd); int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); + int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int page, int cached, int raw); int chip_delay; unsigned int options; @@ -374,7 +401,7 @@ struct nand_chip { struct nand_ecclayout *ecclayout; struct nand_ecc_ctrl ecc; - struct nand_buffers buffers; + struct nand_buffers *buffers; struct nand_hw_control hwcontrol; struct mtd_oob_ops ops; @@ -401,7 +428,6 @@ struct nand_chip { /** * struct nand_flash_dev - NAND Flash Device ID Structure - * * @name: Identify the device type * @id: device ID code * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 @@ -520,9 +546,8 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, /** * struct platform_nand_chip - chip level device structure - * * @nr_chips: max. number of chips to scan for - * @chip_offs: chip number offset + * @chip_offset: chip number offset * @nr_partitions: number of partitions pointed to by partitions (or zero) * @partitions: mtd partition list * @chip_delay: R/B delay value in us @@ -543,11 +568,10 @@ struct platform_nand_chip { /** * struct platform_nand_ctrl - controller level device structure - * * @hwcontrol: platform specific hardware control structure * @dev_ready: platform specific function to read ready/busy pin * @select_chip: platform specific chip select function - * @priv_data: private data to transport driver specific settings + * @priv: private data to transport driver specific settings * * All fields are optional and depend on the hardware driver requirements */