X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-mips%2Fsystem.h;h=76339165bc20e90e84089f8da7fb795f9b9b00c2;hb=c41917df8a1adde34864116ce2231a7fe308d2ff;hp=290887077e4497cda1812a13da6b24d5fd07d243;hpb=c334ba9e11849f0f23254d82a3305f6174cfbd95;p=linux-2.6 diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 290887077e..76339165bc 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -44,7 +44,7 @@ struct task_struct; * different thread. */ -#define switch_to(prev,next,last) \ +#define __mips_mt_fpaff_switch_to(prev) \ do { \ if (cpu_has_fpu && \ (prev->thread.mflags & MF_FPUBOUND) && \ @@ -52,34 +52,24 @@ do { \ prev->thread.mflags &= ~MF_FPUBOUND; \ prev->cpus_allowed = prev->thread.user_cpus_allowed; \ } \ - if (cpu_has_dsp) \ - __save_dsp(prev); \ next->thread.emulated_fp = 0; \ - (last) = resume(prev, next, next->thread_info); \ - if (cpu_has_dsp) \ - __restore_dsp(current); \ } while(0) #else +#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0) +#endif + #define switch_to(prev,next,last) \ do { \ + __mips_mt_fpaff_switch_to(prev); \ if (cpu_has_dsp) \ __save_dsp(prev); \ (last) = resume(prev, next, task_thread_info(next)); \ if (cpu_has_dsp) \ __restore_dsp(current); \ + if (cpu_has_userlocal) \ + write_c0_userlocal(task_thread_info(current)->tp_value);\ } while(0) -#endif - -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { @@ -201,7 +191,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz } #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) #define __HAVE_ARCH_CMPXCHG 1 @@ -262,6 +251,58 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, return retval; } +static inline unsigned long __cmpxchg_u32_local(volatile int * m, + unsigned long old, unsigned long new) +{ + __u32 retval; + + if (cpu_has_llsc && R10000_LLSC_WAR) { + __asm__ __volatile__( + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: ll %0, %2 # __cmpxchg_u32 \n" + " bne %0, %z3, 2f \n" + " .set mips0 \n" + " move $1, %z4 \n" + " .set mips3 \n" + " sc $1, %1 \n" + " beqzl $1, 1b \n" + "2: \n" + " .set pop \n" + : "=&r" (retval), "=R" (*m) + : "R" (*m), "Jr" (old), "Jr" (new) + : "memory"); + } else if (cpu_has_llsc) { + __asm__ __volatile__( + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: ll %0, %2 # __cmpxchg_u32 \n" + " bne %0, %z3, 2f \n" + " .set mips0 \n" + " move $1, %z4 \n" + " .set mips3 \n" + " sc $1, %1 \n" + " beqz $1, 1b \n" + "2: \n" + " .set pop \n" + : "=&r" (retval), "=R" (*m) + : "R" (*m), "Jr" (old), "Jr" (new) + : "memory"); + } else { + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); /* implies memory barrier */ + } + + return retval; +} + #ifdef CONFIG_64BIT static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, unsigned long new) @@ -315,10 +356,62 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, return retval; } + +static inline unsigned long __cmpxchg_u64_local(volatile int * m, + unsigned long old, unsigned long new) +{ + __u64 retval; + + if (cpu_has_llsc && R10000_LLSC_WAR) { + __asm__ __volatile__( + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: lld %0, %2 # __cmpxchg_u64 \n" + " bne %0, %z3, 2f \n" + " move $1, %z4 \n" + " scd $1, %1 \n" + " beqzl $1, 1b \n" + "2: \n" + " .set pop \n" + : "=&r" (retval), "=R" (*m) + : "R" (*m), "Jr" (old), "Jr" (new) + : "memory"); + } else if (cpu_has_llsc) { + __asm__ __volatile__( + " .set push \n" + " .set noat \n" + " .set mips3 \n" + "1: lld %0, %2 # __cmpxchg_u64 \n" + " bne %0, %z3, 2f \n" + " move $1, %z4 \n" + " scd $1, %1 \n" + " beqz $1, 1b \n" + "2: \n" + " .set pop \n" + : "=&r" (retval), "=R" (*m) + : "R" (*m), "Jr" (old), "Jr" (new) + : "memory"); + } else { + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); /* implies memory barrier */ + } + + return retval; +} + #else extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels( volatile int * m, unsigned long old, unsigned long new); #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels +extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels( + volatile int * m, unsigned long old, unsigned long new); +#define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels #endif /* This function doesn't exist, so you'll get a linker error @@ -338,11 +431,33 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, return old; } -#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) +static inline unsigned long __cmpxchg_local(volatile void * ptr, + unsigned long old, unsigned long new, int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32_local(ptr, old, new); + case 8: + return __cmpxchg_u64_local(ptr, old, new); + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr,old,new) \ + ((__typeof__(*(ptr)))__cmpxchg((ptr), \ + (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) + +#define cmpxchg_local(ptr,old,new) \ + ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \ + (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) extern void set_handler (unsigned long offset, void *addr, unsigned long len); extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len); -extern void *set_vi_handler (int n, void *addr); + +typedef void (*vi_handler_t)(void); +extern void *set_vi_handler (int n, vi_handler_t addr); + extern void *set_except_vector(int n, void *addr); extern unsigned long ebase; extern void per_cpu_trap_init(void);