X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-mips%2Fsmtc.h;h=3639b28f80db84acbdea9672eb705fa8976aca7d;hb=d9c566198bfdf72a041322a093fdc1a2dc231170;hp=44dfa4adecf323e970fcdd17d6c1aed8e67ab32e;hpb=9333907084da2b05db787dba3e714d0be7c84f36;p=linux-2.6

diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adec..3639b28f80 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -44,6 +44,7 @@ extern int mipsmt_build_cpu_map(int startslot);
 extern void mipsmt_prepare_cpus(void);
 extern void smtc_smp_finish(void);
 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
+extern void smtc_cpus_done(void);
 
 /*
  * Sharing the TLB between multiple VPEs means that the
@@ -55,4 +56,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
 
 #define PARKED_INDEX	((unsigned int)0x80000000)
 
+/*
+ * Define low-level interrupt mask for IPIs, if necessary.
+ * By default, use SW interrupt 1, which requires no external
+ * hardware support, but which works only for single-core
+ * MIPS MT systems.
+ */
+#ifndef MIPS_CPU_IPI_IRQ
+#define MIPS_CPU_IPI_IRQ 1
+#endif
+
 #endif /*  _ASM_SMTC_MT_H */