X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-blackfin%2Fcplb.h;h=5b0da9a69b6714529f38b759b9145d898f5bbb60;hb=886c35fbcf6fb2eee15687efc2d64d99b6ad9a4a;hp=c9fc77684fb2ec6569391d9498dbec6b3a00cc88;hpb=3bebca2d20796dd3dc62c5d3e74148087c7ce5bd;p=linux-2.6 diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index c9fc77684f..5b0da9a69b 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -30,7 +30,8 @@ #ifndef _CPLB_H #define _CPLB_H -# include +#include +#include #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) @@ -54,6 +55,7 @@ #endif #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) +#define L2_MEMORY (CPLB_COMMON) #define SDRAM_DNON_CHBL (CPLB_COMMON) #define SDRAM_EBIU (CPLB_COMMON) #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) @@ -63,30 +65,14 @@ #define SIZE_1M 0x00100000 /* 1M */ #define SIZE_4M 0x00400000 /* 4M */ +#ifdef CONFIG_MPU +#define MAX_CPLBS 16 +#else #define MAX_CPLBS (16 * 2) +#endif -/* -* Number of required data CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 16 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Data Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -* 1 for ASYNC Memory -*/ - - -#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2) - -/* -* Number of required instruction CPLB switchtable entries -* MEMSIZE / 4 (we mostly install 4M page size CPLBs -* approx 12 for smaller 1MB page size CPLBs for allignment purposes -* 1 for L1 Instruction Memory -* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO -*/ - -#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2) - +#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \ + ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M) #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1