X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-arm%2Ftlbflush.h;h=8c6bc1bb9d1a5cb83c0abe7359841c1c48011bf0;hb=bec95aab8c056ab490fe7fa54da822938562443d;hp=71be4fded7e20f1b069f2dbe7ad3c6a5d63456ca;hpb=08f3dfe8c4b91189890019d307aad236c3633515;p=linux-2.6

diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 71be4fded7..8c6bc1bb9d 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -463,11 +463,6 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
  */
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
 
-/*
- * ARM processors do not cache TLB tables in RAM.
- */
-#define flush_tlb_pgtables(mm,start,end)	do { } while (0)
-
 #endif
 
 #endif /* CONFIG_MMU */