X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=include%2Fasm-arm%2Fhardware%2Fiop3xx.h;h=63feceb7ede558afe103496036f46cfb7195924b;hb=334d0dd8b660557608142f0f77abc6812b48f08b;hp=1018a7486ab76fc717ec2e92096642e54c6b7a05;hpb=7ff3e52cf2947ebd38c84159af68e5a29d228f6c;p=linux-2.6 diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h index 1018a7486a..63feceb7ed 100644 --- a/include/asm-arm/hardware/iop3xx.h +++ b/include/asm-arm/hardware/iop3xx.h @@ -28,6 +28,7 @@ extern void gpio_line_config(int line, int direction); extern int gpio_line_get(int line); extern void gpio_line_set(int line, int value); +extern int init_atu; #endif @@ -37,6 +38,13 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 #define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000 #define IOP3XX_PERIPHERAL_SIZE 0x00002000 +#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\ + IOP3XX_PERIPHERAL_SIZE - 1) +#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ + IOP3XX_PERIPHERAL_SIZE - 1) +#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\ + (IOP3XX_PERIPHERAL_PHYS_BASE\ + - IOP3XX_PERIPHERAL_VIRT_BASE)) #define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) /* Address Translation Unit */ @@ -96,6 +104,21 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) +#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15) +#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14) +#define IOP3XX_ATUCR_OUT_EN (1 << 1) + +#define IOP3XX_INIT_ATU_DEFAULT 0 +#define IOP3XX_INIT_ATU_DISABLE -1 +#define IOP3XX_INIT_ATU_ENABLE 1 + +#ifdef CONFIG_IOP3XX_ATU +#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ + IOP3XX_INIT_ATU_ENABLE : init_atu) +#else +#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\ + IOP3XX_INIT_ATU_DISABLE : init_atu) +#endif /* Messaging Unit */ #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) @@ -168,9 +191,9 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) /* General Purpose I/O */ -#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004) -#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008) -#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x000c) +#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0000) +#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0004) +#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x0008) /* Timers */ #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) @@ -181,14 +204,10 @@ extern void gpio_line_set(int line, int value); #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) -#define IOP3XX_TMR_TC 0x01 -#define IOP3XX_TMR_EN 0x02 -#define IOP3XX_TMR_RELOAD 0x04 -#define IOP3XX_TMR_PRIVILEGED 0x09 -#define IOP3XX_TMR_RATIO_1_1 0x00 -#define IOP3XX_TMR_RATIO_4_1 0x10 -#define IOP3XX_TMR_RATIO_8_1 0x20 -#define IOP3XX_TMR_RATIO_16_1 0x30 +#define IOP_TMR_EN 0x02 +#define IOP_TMR_RELOAD 0x04 +#define IOP_TMR_PRIVILEGED 0x08 +#define IOP_TMR_RATIO_1_1 0x00 /* Application accelerator unit */ #define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800) @@ -250,51 +269,69 @@ extern void gpio_line_set(int line, int value); /* * IOP3XX I/O and Mem space regions for PCI autoconfiguration */ -#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 -#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 -#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0) +#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 #define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 #define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 -#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR) +#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 +#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ + IOP3XX_PCI_IO_WINDOW_SIZE - 1) +#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ + IOP3XX_PCI_IO_WINDOW_SIZE - 1) +#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) addr -\ + IOP3XX_PCI_LOWER_IO_PA) +\ + IOP3XX_PCI_LOWER_IO_VA) #ifndef __ASSEMBLY__ void iop3xx_map_io(void); -void iop3xx_init_time(unsigned long); -unsigned long iop3xx_gettimeoffset(void); +void iop_init_cp6_handler(void); +void iop_init_time(unsigned long tickrate); +unsigned long iop_gettimeoffset(void); -extern struct platform_device iop3xx_i2c0_device; -extern struct platform_device iop3xx_i2c1_device; +static inline void write_tmr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); +} + +static inline void write_tmr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); +} -extern inline void iop3xx_cp6_enable(void) +static inline u32 read_tcr0(void) { - u32 temp; - - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4\n\t" - : "=r" (temp) ); + u32 val; + asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); + return val; } -extern inline void iop3xx_cp6_disable(void) +static inline u32 read_tcr1(void) { - u32 temp; - - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "bic %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4\n\t" - : "=r" (temp) ); + u32 val; + asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); + return val; } + +static inline void write_trr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); +} + +static inline void write_trr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); +} + +static inline void write_tisr(u32 val) +{ + asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); +} + +extern struct platform_device iop3xx_i2c0_device; +extern struct platform_device iop3xx_i2c1_device; + #endif