X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fpci%2Fprobe.c;h=3706ce7972dddc0c389f828a3ec0c4635d1d8efe;hb=f086f23435bf42f700296f1be3878f6aa6e9b7dd;hp=07d5c7424b0198947023101021b8f1cef7802b88;hpb=cb3576fa34e36907e292f408cb6c258f4fd112ad;p=linux-2.6 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 07d5c7424b..3706ce7972 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "pci.h" #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ @@ -91,6 +92,7 @@ void pci_remove_legacy_files(struct pci_bus *bus) { return; } * PCI Bus Class Devices */ static ssize_t pci_bus_show_cpuaffinity(struct device *dev, + int type, struct device_attribute *attr, char *buf) { @@ -98,12 +100,30 @@ static ssize_t pci_bus_show_cpuaffinity(struct device *dev, cpumask_t cpumask; cpumask = pcibus_to_cpumask(to_pci_bus(dev)); - ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask); - if (ret < PAGE_SIZE) - buf[ret++] = '\n'; + ret = type? + cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask): + cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask); + buf[ret++] = '\n'; + buf[ret] = '\0'; return ret; } -DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL); + +static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return pci_bus_show_cpuaffinity(dev, 0, attr, buf); +} + +static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return pci_bus_show_cpuaffinity(dev, 1, attr, buf); +} + +DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL); +DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL); /* * PCI Bus Class @@ -234,7 +254,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; } res->end = res->start + (unsigned long) sz; - res->flags |= pci_calc_resource_flags(l); + res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; if (is_64bit_memory(l)) { u32 szhi, lhi; @@ -287,7 +307,8 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) if (sz) { res->flags = (l & IORESOURCE_ROM_ENABLE) | IORESOURCE_MEM | IORESOURCE_PREFETCH | - IORESOURCE_READONLY | IORESOURCE_CACHEABLE; + IORESOURCE_READONLY | IORESOURCE_CACHEABLE | + IORESOURCE_SIZEALIGN; res->start = l & PCI_ROM_ADDRESS_MASK; res->end = res->start + (unsigned long) sz; } @@ -397,8 +418,8 @@ static struct pci_bus * pci_alloc_bus(void) return b; } -static struct pci_bus * __devinit -pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) +static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, + struct pci_dev *bridge, int busnr) { struct pci_bus *child; int i; @@ -793,6 +814,7 @@ static void pci_release_dev(struct device *dev) struct pci_dev *pci_dev; pci_dev = to_pci_dev(dev); + pci_vpd_release(pci_dev); kfree(pci_dev); } @@ -820,6 +842,21 @@ static void set_pcie_port_type(struct pci_dev *pdev) * reading the dword at 0x100 which must either be 0 or a valid extended * capability header. */ +int pci_cfg_space_size_ext(struct pci_dev *dev) +{ + u32 status; + + if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) + goto fail; + if (status == 0xffffffff) + goto fail; + + return PCI_CFG_SPACE_EXP_SIZE; + + fail: + return PCI_CFG_SPACE_SIZE; +} + int pci_cfg_space_size(struct pci_dev *dev) { int pos; @@ -836,12 +873,7 @@ int pci_cfg_space_size(struct pci_dev *dev) goto fail; } - if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL) - goto fail; - if (status == 0xffffffff) - goto fail; - - return PCI_CFG_SPACE_EXP_SIZE; + return pci_cfg_space_size_ext(dev); fail: return PCI_CFG_SPACE_SIZE; @@ -872,8 +904,7 @@ EXPORT_SYMBOL(alloc_pci_dev); * Read the config data for a PCI device, sanity-check it * and fill in the dev structure... */ -static struct pci_dev * __devinit -pci_scan_device(struct pci_bus *bus, int devfn) +static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) { struct pci_dev *dev; u32 l; @@ -932,6 +963,8 @@ pci_scan_device(struct pci_bus *bus, int devfn) return NULL; } + pci_vpd_pci22_init(dev); + return dev; } @@ -941,7 +974,6 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) dev->dev.release = pci_release_dev; pci_dev_get(dev); - set_dev_node(&dev->dev, pcibus_to_node(bus)); dev->dev.dma_mask = &dev->dma_mask; dev->dev.dma_parms = &dev->dma_parms; dev->dev.coherent_dma_mask = 0xffffffffull; @@ -1014,6 +1046,10 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) break; } } + + if (bus->self) + pcie_aspm_init_link_state(bus->self); + return nr; } @@ -1053,6 +1089,10 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) return max; } +void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b) +{ +} + struct pci_bus * pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata) { @@ -1092,6 +1132,9 @@ struct pci_bus * pci_create_bus(struct device *parent, goto dev_reg_err; b->bridge = get_device(dev); + if (!parent) + set_dev_node(b->bridge, pcibus_to_node(b)); + b->dev.class = &pcibus_class; b->dev.parent = b->bridge; sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); @@ -1109,6 +1152,8 @@ struct pci_bus * pci_create_bus(struct device *parent, b->resource[0] = &ioport_resource; b->resource[1] = &iomem_resource; + set_pci_bus_resources_arch_default(b); + return b; dev_create_file_err: