X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fwireless%2Fiwlwifi%2Fiwl-3945.c;h=39e7b07248cd32075ae56d4954dc5fec068ab706;hb=c8b0e6e19c0bcd30689cb6c6f64eb140f5d61894;hp=3a45fe99a83e72c4a3786787e347e12f4a480103;hpb=d89a9bda14204547f966ed1510a269a44c0b7f5d;p=linux-2.6 diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index 3a45fe99a8..39e7b07248 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c @@ -39,11 +39,8 @@ #include -#define IWL 3945 - -#include "iwlwifi.h" -#include "iwl-helpers.h" #include "iwl-3945.h" +#include "iwl-helpers.h" #include "iwl-3945-rs.h" #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ @@ -96,7 +93,7 @@ const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { * ... and set IWL_EVT_DISABLE to 1. */ void iwl_disable_events(struct iwl_priv *priv) { - int rc; + int ret; int i; u32 base; /* SRAM address of event log header */ u32 disable_ptr; /* SRAM address of event-disable bitmap array */ @@ -157,27 +154,26 @@ void iwl_disable_events(struct iwl_priv *priv) return; } - rc = iwl_grab_restricted_access(priv); - if (rc) { + ret = iwl_grab_nic_access(priv); + if (ret) { IWL_WARNING("Can not read from adapter at this time.\n"); return; } - disable_ptr = iwl_read_restricted_mem(priv, base + (4 * sizeof(u32))); - array_size = iwl_read_restricted_mem(priv, base + (5 * sizeof(u32))); - iwl_release_restricted_access(priv); + disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32))); + array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32))); + iwl_release_nic_access(priv); if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", disable_ptr); - rc = iwl_grab_restricted_access(priv); + ret = iwl_grab_nic_access(priv); for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) - iwl_write_restricted_mem(priv, - disable_ptr + - (i * sizeof(u32)), - evt_disable[i]); + iwl_write_targ_mem(priv, + disable_ptr + (i * sizeof(u32)), + evt_disable[i]); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); } else { IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); @@ -375,7 +371,7 @@ static void iwl3945_rx_reply_rx(struct iwl_priv *priv, network_packet = iwl_is_network_packet(priv, header); -#ifdef CONFIG_IWLWIFI_DEBUG +#ifdef CONFIG_IWL3945_DEBUG if (iwl_debug_level & IWL_DL_STATS && net_ratelimit()) IWL_DEBUG_STATS ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n", @@ -526,14 +522,14 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, } /** - * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.last_used] + * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr] * * Does NOT advance any indexes */ int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) { struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0]; - struct iwl_tfd_frame *bd = &bd_tmp[txq->q.last_used]; + struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; struct pci_dev *dev = priv->pci_dev; int i; int counter; @@ -556,12 +552,12 @@ int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) for (i = 1; i < counter; i++) { pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr), le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE); - if (txq->txb[txq->q.last_used].skb[0]) { - struct sk_buff *skb = txq->txb[txq->q.last_used].skb[0]; - if (txq->txb[txq->q.last_used].skb[0]) { + if (txq->txb[txq->q.read_ptr].skb[0]) { + struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0]; + if (txq->txb[txq->q.read_ptr].skb[0]) { /* Can be called from interrupt context */ dev_kfree_skb_any(skb); - txq->txb[txq->q.last_used].skb[0] = NULL; + txq->txb[txq->q.read_ptr].skb[0] = NULL; } } } @@ -700,28 +696,13 @@ u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags) return sta_id; } -void iwl_hw_card_show_info(struct iwl_priv *priv) -{ - IWL_DEBUG_INFO("3945ABG HW Version %u.%u.%u\n", - ((priv->eeprom.board_revision >> 8) & 0x0F), - ((priv->eeprom.board_revision >> 8) >> 4), - (priv->eeprom.board_revision & 0x00FF)); - - IWL_DEBUG_INFO("3945ABG PBA Number %.*s\n", - (int)sizeof(priv->eeprom.board_pba_number), - priv->eeprom.board_pba_number); - - IWL_DEBUG_INFO("EEPROM_ANTENNA_SWITCH_TYPE is 0x%02X\n", - priv->eeprom.antenna_switch_type); -} - static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) { int rc; unsigned long flags; spin_lock_irqsave(&priv->lock, flags); - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; @@ -733,22 +714,22 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) rc = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE, &val); if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { - iwl_set_bits_mask_restricted_reg(priv, APMG_PS_CTRL_REG, + iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_PWR_SRC_VAUX, ~APMG_PS_CTRL_MSK_PWR_SRC); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VAUX_PWR_SRC, CSR_GPIO_IN_BIT_AUX_POWER, 5000); } else - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); } else { - iwl_set_bits_mask_restricted_reg(priv, APMG_PS_CTRL_REG, + iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~APMG_PS_CTRL_MSK_PWR_SRC); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ } @@ -763,18 +744,18 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) unsigned long flags; spin_lock_irqsave(&priv->lock, flags); - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; } - iwl_write_restricted(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); - iwl_write_restricted(priv, FH_RCSR_RPTR_ADDR(0), + iwl_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); + iwl_write_direct32(priv, FH_RCSR_RPTR_ADDR(0), priv->hw_setting.shared_phys + offsetof(struct iwl_shared, rx_read_ptr[0])); - iwl_write_restricted(priv, FH_RCSR_WPTR(0), 0); - iwl_write_restricted(priv, FH_RCSR_CONFIG(0), + iwl_write_direct32(priv, FH_RCSR_WPTR(0), 0); + iwl_write_direct32(priv, FH_RCSR_CONFIG(0), ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | @@ -785,9 +766,9 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); /* fake read to flush all prev I/O */ - iwl_read_restricted(priv, FH_RSSR_CTRL); + iwl_read_direct32(priv, FH_RSSR_CTRL); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); spin_unlock_irqrestore(&priv->lock, flags); return 0; @@ -799,30 +780,30 @@ static int iwl3945_tx_reset(struct iwl_priv *priv) unsigned long flags; spin_lock_irqsave(&priv->lock, flags); - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; } /* bypass mode */ - iwl_write_restricted_reg(priv, SCD_MODE_REG, 0x2); + iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2); /* RA 0 is active */ - iwl_write_restricted_reg(priv, SCD_ARASTAT_REG, 0x01); + iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); /* all 6 fifo are active */ - iwl_write_restricted_reg(priv, SCD_TXFACT_REG, 0x3f); + iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); - iwl_write_restricted_reg(priv, SCD_SBYP_MODE_1_REG, 0x010000); - iwl_write_restricted_reg(priv, SCD_SBYP_MODE_2_REG, 0x030002); - iwl_write_restricted_reg(priv, SCD_TXF4MF_REG, 0x000004); - iwl_write_restricted_reg(priv, SCD_TXF5MF_REG, 0x000005); + iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); + iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); + iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); + iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); - iwl_write_restricted(priv, FH_TSSR_CBB_BASE, + iwl_write_direct32(priv, FH_TSSR_CBB_BASE, priv->hw_setting.shared_phys); - iwl_write_restricted(priv, FH_TSSR_MSG_CONFIG, + iwl_write_direct32(priv, FH_TSSR_MSG_CONFIG, ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | @@ -831,7 +812,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv) ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); spin_unlock_irqrestore(&priv->lock, flags); return 0; @@ -897,18 +878,18 @@ int iwl_hw_nic_init(struct iwl_priv *priv) return rc; } - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; } - iwl_write_restricted_reg(priv, APMG_CLK_EN_REG, + iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT); udelay(20); - iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG, + iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, APMG_PCIDEV_STT_VAL_L1_ACT_DIS); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); spin_unlock_irqrestore(&priv->lock, flags); /* Determine HW type */ @@ -999,13 +980,13 @@ int iwl_hw_nic_init(struct iwl_priv *priv) iwl_rx_queue_update_write_ptr(priv, rxq); */ - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; } - iwl_write_restricted(priv, FH_RCSR_WPTR(0), rxq->write & ~7); - iwl_release_restricted_access(priv); + iwl_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7); + iwl_release_nic_access(priv); spin_unlock_irqrestore(&priv->lock, flags); @@ -1038,24 +1019,24 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv) unsigned long flags; spin_lock_irqsave(&priv->lock, flags); - if (iwl_grab_restricted_access(priv)) { + if (iwl_grab_nic_access(priv)) { spin_unlock_irqrestore(&priv->lock, flags); iwl_hw_txq_ctx_free(priv); return; } /* stop SCD */ - iwl_write_restricted_reg(priv, SCD_MODE_REG, 0); + iwl_write_prph(priv, ALM_SCD_MODE_REG, 0); /* reset TFD queues */ for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { - iwl_write_restricted(priv, FH_TCSR_CONFIG(queue), 0x0); - iwl_poll_restricted_bit(priv, FH_TSSR_TX_STATUS, + iwl_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0); + iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS, ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue), 1000); } - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); spin_unlock_irqrestore(&priv->lock, flags); iwl_hw_txq_ctx_free(priv); @@ -1109,9 +1090,9 @@ int iwl_hw_nic_reset(struct iwl_priv *priv) CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (!rc) { - iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG, + iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_BSM_CLK_RQT); udelay(10); @@ -1119,22 +1100,22 @@ int iwl_hw_nic_reset(struct iwl_priv *priv) iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); - iwl_write_restricted_reg(priv, APMG_RTC_INT_MSK_REG, 0x0); - iwl_write_restricted_reg(priv, APMG_RTC_INT_STT_REG, + iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); + iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF); /* enable DMA */ - iwl_write_restricted_reg(priv, APMG_CLK_EN_REG, + iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT); udelay(10); - iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG, + iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); udelay(5); - iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG, + iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); } /* Clear the 'host command active' bit... */ @@ -1147,8 +1128,9 @@ int iwl_hw_nic_reset(struct iwl_priv *priv) } /** - * iwl_hw_reg_adjust_power_by_temp - return index delta into power gain settings table - */ + * iwl_hw_reg_adjust_power_by_temp + * return index delta into power gain settings table +*/ static int iwl_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) { return (new_reading - old_reading) * (-11) / 100; @@ -1168,8 +1150,9 @@ int iwl_hw_get_temperature(struct iwl_priv *priv) } /** - * iwl_hw_reg_txpower_get_temperature - get current temperature by reading from NIC - */ + * iwl_hw_reg_txpower_get_temperature + * get the current temperature by reading from NIC +*/ static int iwl_hw_reg_txpower_get_temperature(struct iwl_priv *priv) { int temperature; @@ -1779,7 +1762,7 @@ void iwl3945_reg_txpower_periodic(struct iwl_priv *priv) &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ); } -void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) +static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) { struct iwl_priv *priv = container_of(work, struct iwl_priv, thermal_periodic.work); @@ -2095,18 +2078,18 @@ int iwl_hw_rxq_stop(struct iwl_priv *priv) unsigned long flags; spin_lock_irqsave(&priv->lock, flags); - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; } - iwl_write_restricted(priv, FH_RCSR_CONFIG(0), 0); - rc = iwl_poll_restricted_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000); + iwl_write_direct32(priv, FH_RCSR_CONFIG(0), 0); + rc = iwl_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000); if (rc < 0) IWL_ERROR("Can't stop Rx DMA.\n"); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); spin_unlock_irqrestore(&priv->lock, flags); return 0; @@ -2123,21 +2106,21 @@ int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); spin_lock_irqsave(&priv->lock, flags); - rc = iwl_grab_restricted_access(priv); + rc = iwl_grab_nic_access(priv); if (rc) { spin_unlock_irqrestore(&priv->lock, flags); return rc; } - iwl_write_restricted(priv, FH_CBCC_CTRL(txq_id), 0); - iwl_write_restricted(priv, FH_CBCC_BASE(txq_id), 0); + iwl_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0); + iwl_write_direct32(priv, FH_CBCC_BASE(txq_id), 0); - iwl_write_restricted(priv, FH_TCSR_CONFIG(txq_id), + iwl_write_direct32(priv, FH_TCSR_CONFIG(txq_id), ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); - iwl_release_restricted_access(priv); + iwl_release_nic_access(priv); /* fake read to flush all prev. writes */ iwl_read32(priv, FH_TSSR_CBB_BASE); @@ -2240,7 +2223,6 @@ int iwl_hw_set_hw_setting(struct iwl_priv *priv) priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd); priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE; priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG; - priv->hw_setting.cck_flag = 0; priv->hw_setting.max_stations = IWL3945_STATION_COUNT; priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID; return 0; @@ -2297,12 +2279,12 @@ void iwl_hw_cancel_deferred_work(struct iwl_priv *priv) } struct pci_device_id iwl_hw_card_ids[] = { - {0x8086, 0x4222, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, - {0x8086, 0x4227, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, + {PCI_DEVICE(0x8086, 0x4222)}, + {PCI_DEVICE(0x8086, 0x4227)}, {0} }; -inline int iwl_eeprom_aqcuire_semaphore(struct iwl_priv *priv) +inline int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv) { _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); return 0;