X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fwireless%2Fbcm43xx%2Fbcm43xx.h;h=8286678513b937db84bbfebff057191a62a0bdab;hb=47c93d2faf9d7e94393852823480ea61c868caee;hp=6d4ea36bc5644753b8933deedb8222ca83afc957;hpb=cb930205c9dc26efedba5e93e6f84b98f36257e1;p=linux-2.6 diff --git a/drivers/net/wireless/bcm43xx/bcm43xx.h b/drivers/net/wireless/bcm43xx/bcm43xx.h index 6d4ea36bc5..10e07e8654 100644 --- a/drivers/net/wireless/bcm43xx/bcm43xx.h +++ b/drivers/net/wireless/bcm43xx/bcm43xx.h @@ -21,7 +21,7 @@ #define PFX KBUILD_MODNAME ": " #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50 -#define BCM43xx_IRQWAIT_MAX_RETRIES 50 +#define BCM43xx_IRQWAIT_MAX_RETRIES 100 #define BCM43xx_IO_SIZE 8192 @@ -159,6 +159,7 @@ /* Chipcommon registers. */ #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 +#define BCM43xx_CHIPCOMMON_CTL 0x28 #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 @@ -172,6 +173,33 @@ /* SBTOPCI2 values. */ #define BCM43xx_SBTOPCI2_PREFETCH 0x4 #define BCM43xx_SBTOPCI2_BURST 0x8 +#define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20 + +/* PCI-E core registers. */ +#define BCM43xx_PCIECORE_REG_ADDR 0x0130 +#define BCM43xx_PCIECORE_REG_DATA 0x0134 +#define BCM43xx_PCIECORE_MDIO_CTL 0x0128 +#define BCM43xx_PCIECORE_MDIO_DATA 0x012C + +/* PCI-E registers. */ +#define BCM43xx_PCIE_TLP_WORKAROUND 0x0004 +#define BCM43xx_PCIE_DLLP_LINKCTL 0x0100 + +/* PCI-E MDIO bits. */ +#define BCM43xx_PCIE_MDIO_ST 0x40000000 +#define BCM43xx_PCIE_MDIO_WT 0x10000000 +#define BCM43xx_PCIE_MDIO_DEV 22 +#define BCM43xx_PCIE_MDIO_REG 18 +#define BCM43xx_PCIE_MDIO_TA 0x00020000 +#define BCM43xx_PCIE_MDIO_TC 0x0100 + +/* MDIO devices. */ +#define BCM43xx_MDIO_SERDES_RX 0x1F + +/* SERDES RX registers. */ +#define BCM43xx_SERDES_RXTIMER 0x2 +#define BCM43xx_SERDES_CDR 0x6 +#define BCM43xx_SERDES_CDR_BW 0x7 /* Chipcommon capabilities. */ #define BCM43xx_CAPABILITIES_PCTL 0x00040000 @@ -221,6 +249,7 @@ #define BCM43xx_COREID_USB20_HOST 0x819 #define BCM43xx_COREID_USB20_DEV 0x81a #define BCM43xx_COREID_SDIO_HOST 0x81b +#define BCM43xx_COREID_PCIE 0x820 /* Core Information Registers */ #define BCM43xx_CIR_BASE 0xf00 @@ -248,11 +277,14 @@ #define BCM43xx_SBTMSTATELOW_REJECT 0x02 #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000 +#define BCM43xx_SBTMSTATELOW_G_MODE_ENABLE 0x20000000 /* sbtmstatehigh state flags */ #define BCM43xx_SBTMSTATEHIGH_SERROR 0x00000001 #define BCM43xx_SBTMSTATEHIGH_BUSY 0x00000004 #define BCM43xx_SBTMSTATEHIGH_TIMEOUT 0x00000020 +#define BCM43xx_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000 +#define BCM43xx_SBTMSTATEHIGH_A_PHY_AVAIL 0x00020000 #define BCM43xx_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000 #define BCM43xx_SBTMSTATEHIGH_DMA64BIT 0x10000000 #define BCM43xx_SBTMSTATEHIGH_GATEDCLK 0x20000000 @@ -304,7 +336,7 @@ #define BCM43xx_SBF_PS2 0x04000000 #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000 #define BCM43xx_SBF_TIME_UPDATE 0x10000000 -#define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/ +#define BCM43xx_SBF_MODE_G 0x80000000 /* Microcode */ #define BCM43xx_UCODE_REVISION 0x0000 @@ -323,6 +355,10 @@ #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040 #define BCM43xx_UCODEFLAG_JAPAN 0x0080 +/* Hardware Radio Enable masks */ +#define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) +#define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) + /* Generic-Interrupt reasons. */ #define BCM43xx_IRQ_READY (1 << 0) #define BCM43xx_IRQ_BEACON (1 << 1) @@ -365,6 +401,9 @@ #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 +/* FIXME: the next line is a guess as to what the maximum RSSI value might be */ +#define RX_RSSI_MAX 60 + /* Max size of a security key */ #define BCM43xx_SEC_KEYSIZE 16 /* Security algorithms. */ @@ -471,8 +510,6 @@ struct bcm43xx_sprominfo { u8 et1macaddr[6]; u8 et0phyaddr:5; u8 et1phyaddr:5; - u8 et0mdcport:1; - u8 et1mdcport:1; u8 boardrev; u8 locale:4; u8 antennas_aphy:2; @@ -506,7 +543,7 @@ struct bcm43xx_lopair { struct bcm43xx_phyinfo { /* Hardware Data */ - u8 version; + u8 analog; u8 type; u8 rev; u16 antenna_diversity; @@ -621,12 +658,6 @@ struct bcm43xx_pio { #define BCM43xx_MAX_80211_CORES 2 -#ifdef CONFIG_BCM947XX -#define core_offset(bcm) (bcm)->current_core_offset -#else -#define core_offset(bcm) 0 -#endif - /* Generic information about a core. */ struct bcm43xx_coreinfo { u8 available:1, @@ -666,7 +697,6 @@ struct bcm43xx_noise_calculation { }; struct bcm43xx_stats { - u8 link_quality; u8 noise; struct iw_statistics wstats; /* Store the last TX/RX times here for updating the leds. */ @@ -727,7 +757,8 @@ struct bcm43xx_private { bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */ reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */ short_preamble:1, /* TRUE, if short preamble is enabled. */ - firmware_norelease:1; /* Do not release the firmware. Used on suspend. */ + firmware_norelease:1, /* Do not release the firmware. Used on suspend. */ + radio_hw_enable:1; /* TRUE if radio is hardware enabled */ struct bcm43xx_stats stats; @@ -735,6 +766,7 @@ struct bcm43xx_private { * This is currently always BCM43xx_BUSTYPE_PCI */ u8 bustype; + u64 dma_mask; u16 board_vendor; u16 board_type; @@ -751,10 +783,6 @@ struct bcm43xx_private { /* The currently active core. */ struct bcm43xx_coreinfo *current_core; -#ifdef CONFIG_BCM947XX - /** current core memory offset */ - u32 current_core_offset; -#endif struct bcm43xx_coreinfo *active_80211_core; /* coreinfo structs for all possible cores follow. * Note that a core might not exist. @@ -788,7 +816,7 @@ struct bcm43xx_private { struct tasklet_struct isr_tasklet; /* Periodic tasks */ - struct work_struct periodic_work; + struct delayed_work periodic_work; unsigned int periodic_state; struct work_struct restart_work; @@ -905,25 +933,25 @@ struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy, static inline u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset) { - return ioread16(bcm->mmio_addr + core_offset(bcm) + offset); + return ioread16(bcm->mmio_addr + offset); } static inline void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value) { - iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset); + iowrite16(value, bcm->mmio_addr + offset); } static inline u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset) { - return ioread32(bcm->mmio_addr + core_offset(bcm) + offset); + return ioread32(bcm->mmio_addr + offset); } static inline void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value) { - iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset); + iowrite32(value, bcm->mmio_addr + offset); } static inline