X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2.h;h=2377cc13bf61afc14d7598eaa93cf78a691204a7;hb=3ea9eed49346eb80f17f1c6539c47dc508be1173;hp=c1ab30b0f87a20b8d2a38a5dd95c15a39bb11266;hpb=2dd201d7b735f252df1a915a3f2e6a71910a3d87;p=linux-2.6 diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index c1ab30b0f8..2377cc13bf 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -348,6 +348,12 @@ struct l2_fhdr { #define BNX2_L2CTX_BD_PRE_READ 0x00000000 #define BNX2_L2CTX_CTX_SIZE 0x00000000 #define BNX2_L2CTX_CTX_TYPE 0x00000000 +#define BNX2_L2CTX_LO_WATER_MARK_DEFAULT 32 +#define BNX2_L2CTX_LO_WATER_MARK_SCALE 4 +#define BNX2_L2CTX_LO_WATER_MARK_DIS 0 +#define BNX2_L2CTX_HI_WATER_MARK_SHIFT 4 +#define BNX2_L2CTX_HI_WATER_MARK_SCALE 16 +#define BNX2_L2CTX_WATER_MARKS_MSK 0x000000ff #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) @@ -4494,6 +4500,9 @@ struct l2_fhdr { #define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31) #define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646 +#define BNX2_MQ_MAP_L2_5 0x00003d34 +#define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26) + /* * tsch_reg definition * offset: 0x4c00 @@ -5510,6 +5519,15 @@ struct l2_fhdr { #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0) #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16) +#define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \ + BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \ + BNX2_HC_SB_CONFIG_1) +#define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1) + /* * txp_reg definition @@ -6344,6 +6362,16 @@ struct l2_fhdr { #define MII_BNX2_DSP_RW_PORT 0x15 #define MII_BNX2_DSP_ADDRESS 0x17 #define MII_BNX2_DSP_EXPAND_REG 0x0f00 +#define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1) +#define MII_EXPAND_REG1_RUDI_C 0x20 +#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 3) + +#define MII_BNX2_MISC_SHADOW 0x1c +#define MISC_SHDW_AN_DBG 0x6800 +#define MISC_SHDW_AN_DBG_NOSYNC 0x0002 +#define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100 +#define MISC_SHDW_MODE_CTL 0x7c00 +#define MISC_SHDW_MODE_CTL_SIG_DET 0x0010 #define MII_BNX2_BLK_ADDR 0x1f #define MII_BNX2_BLK_ADDR_IEEE0 0x0000 @@ -6386,7 +6414,7 @@ struct l2_fhdr { #define RX_COPY_THRESH 128 -#define BNX2_MISC_ENABLE_DEFAULT 0x7ffffff +#define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff #define DMA_READ_CHANS 5 #define DMA_WRITE_CHANS 3 @@ -6571,18 +6599,19 @@ struct bnx2 { atomic_t intr_sem; u32 flags; -#define PCIX_FLAG 0x00000001 -#define PCI_32BIT_FLAG 0x00000002 -#define MSIX_CAP_FLAG 0x00000004 -#define NO_WOL_FLAG 0x00000008 -#define USING_MSI_FLAG 0x00000020 -#define ASF_ENABLE_FLAG 0x00000040 -#define MSI_CAP_FLAG 0x00000080 -#define ONE_SHOT_MSI_FLAG 0x00000100 -#define PCIE_FLAG 0x00000200 -#define USING_MSIX_FLAG 0x00000400 -#define USING_MSI_OR_MSIX_FLAG (USING_MSI_FLAG | USING_MSIX_FLAG) -#define JUMBO_BROKEN_FLAG 0x00000800 +#define BNX2_FLAG_PCIX 0x00000001 +#define BNX2_FLAG_PCI_32BIT 0x00000002 +#define BNX2_FLAG_MSIX_CAP 0x00000004 +#define BNX2_FLAG_NO_WOL 0x00000008 +#define BNX2_FLAG_USING_MSI 0x00000020 +#define BNX2_FLAG_ASF_ENABLE 0x00000040 +#define BNX2_FLAG_MSI_CAP 0x00000080 +#define BNX2_FLAG_ONE_SHOT_MSI 0x00000100 +#define BNX2_FLAG_PCIE 0x00000200 +#define BNX2_FLAG_USING_MSIX 0x00000400 +#define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \ + BNX2_FLAG_USING_MSIX) +#define BNX2_FLAG_JUMBO_BROKEN 0x00000800 /* Put tx producer and consumer fields in separate cache lines. */ @@ -6627,22 +6656,23 @@ struct bnx2 { int current_interval; struct timer_list timer; struct work_struct reset_task; - int in_reset_task; /* Used to synchronize phy accesses. */ spinlock_t phy_lock; spinlock_t indirect_lock; u32 phy_flags; -#define PHY_SERDES_FLAG 1 -#define PHY_CRC_FIX_FLAG 2 -#define PHY_PARALLEL_DETECT_FLAG 4 -#define PHY_2_5G_CAPABLE_FLAG 8 -#define PHY_INT_MODE_MASK_FLAG 0x300 -#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 -#define PHY_INT_MODE_LINK_READY_FLAG 0x200 -#define PHY_DIS_EARLY_DAC_FLAG 0x400 -#define REMOTE_PHY_CAP_FLAG 0x800 +#define BNX2_PHY_FLAG_SERDES 0x00000001 +#define BNX2_PHY_FLAG_CRC_FIX 0x00000002 +#define BNX2_PHY_FLAG_PARALLEL_DETECT 0x00000004 +#define BNX2_PHY_FLAG_2_5G_CAPABLE 0x00000008 +#define BNX2_PHY_FLAG_INT_MODE_MASK 0x00000300 +#define BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING 0x00000100 +#define BNX2_PHY_FLAG_INT_MODE_LINK_READY 0x00000200 +#define BNX2_PHY_FLAG_DIS_EARLY_DAC 0x00000400 +#define BNX2_PHY_FLAG_REMOTE_PHY_CAP 0x00000800 +#define BNX2_PHY_FLAG_FORCED_DOWN 0x00001000 +#define BNX2_PHY_FLAG_NO_PARALLEL 0x00002000 u32 mii_bmcr; u32 mii_bmsr; @@ -6784,9 +6814,6 @@ struct bnx2 { int irq_nvecs; }; -static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset); -static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val); - #define REG_RD(bp, offset) \ readl(bp->regview + offset) @@ -6796,19 +6823,6 @@ static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val); #define REG_WR16(bp, offset, val) \ writew(val, bp->regview + offset) -#define REG_RD_IND(bp, offset) \ - bnx2_reg_rd_ind(bp, offset) - -#define REG_WR_IND(bp, offset, val) \ - bnx2_reg_wr_ind(bp, offset, val) - -/* Indirect context access. Unlike the MBQ_WR, these macros will not - * trigger a chip event. */ -static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val); - -#define CTX_WR(bp, cid_addr, offset, val) \ - bnx2_ctx_wr(bp, cid_addr, offset, val) - struct cpu_reg { u32 mode; u32 mode_value_halt; @@ -6839,7 +6853,7 @@ struct fw_info { const u32 text_addr; const u32 text_len; const u32 text_index; - u32 *text; + __le32 *text; u8 *gz_text; const u32 gz_text_len;