X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=drivers%2Fide%2Fpci%2Fscc_pata.c;h=a19687caf65a6a95c1da40ce4162bf846ee3ed56;hb=f212ff28f08e4ddcef9f25b13463c45cc4204a0c;hp=55bc0a32e34f9d1b8781bef98a34461cce96ade8;hpb=4728d546d7137ad5350cc2e53d4748fd26f61a60;p=linux-2.6 diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c index 55bc0a32e3..a19687caf6 100644 --- a/drivers/ide/pci/scc_pata.c +++ b/drivers/ide/pci/scc_pata.c @@ -165,9 +165,9 @@ scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port) ide_hwif_t *hwif = HWIF(drive); out_be32((void*)port, addr); - __asm__ __volatile__("eieio":::"memory"); + eieio(); in_be32((void*)(hwif->dma_base + 0x01c)); - __asm__ __volatile__("eieio":::"memory"); + eieio(); } static void @@ -190,7 +190,7 @@ scc_ide_outsl(unsigned long port, void *addr, u32 count) } /** - * scc_tuneproc - tune a drive PIO mode + * scc_tune_pio - tune a drive PIO mode * @drive: drive to tune * @mode_wanted: the target operating mode * @@ -198,7 +198,7 @@ scc_ide_outsl(unsigned long port, void *addr, u32 count) * controller. */ -static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted) +static void scc_tune_pio(ide_drive_t *drive, const u8 pio) { ide_hwif_t *hwif = HWIF(drive); struct scc_ports *ports = ide_get_hwifdata(hwif); @@ -207,56 +207,39 @@ static void scc_tuneproc(ide_drive_t *drive, byte mode_wanted) unsigned long piosht_port = ctl_base + 0x000; unsigned long pioct_port = ctl_base + 0x004; unsigned long reg; - unsigned char speed = XFER_PIO_0; int offset; - mode_wanted = ide_get_best_pio_mode(drive, mode_wanted, 4, NULL); - switch (mode_wanted) { - case 4: - speed = XFER_PIO_4; - break; - case 3: - speed = XFER_PIO_3; - break; - case 2: - speed = XFER_PIO_2; - break; - case 1: - speed = XFER_PIO_1; - break; - case 0: - default: - speed = XFER_PIO_0; - break; - } - reg = in_be32((void __iomem *)cckctrl_port); if (reg & CCKCTRL_ATACLKOEN) { offset = 1; /* 133MHz */ } else { offset = 0; /* 100MHz */ } - reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted]; + reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio]; out_be32((void __iomem *)piosht_port, reg); - reg = JCHCTtbl[offset][mode_wanted]; + reg = JCHCTtbl[offset][pio]; out_be32((void __iomem *)pioct_port, reg); +} - ide_config_drive_speed(drive, speed); +static void scc_tuneproc(ide_drive_t *drive, u8 pio) +{ + pio = ide_get_best_pio_mode(drive, pio, 4); + scc_tune_pio(drive, pio); + ide_config_drive_speed(drive, XFER_PIO_0 + pio); } /** * scc_tune_chipset - tune a drive DMA mode * @drive: Drive to set up - * @xferspeed: speed we want to achieve + * @speed: speed we want to achieve * * Load the timing settings for this device mode into the * controller. */ -static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed) +static int scc_tune_chipset(ide_drive_t *drive, const u8 speed) { ide_hwif_t *hwif = HWIF(drive); - u8 speed = ide_rate_filter(drive, xferspeed); struct scc_ports *ports = ide_get_hwifdata(hwif); unsigned long ctl_base = ports->ctl; unsigned long cckctrl_port = ctl_base + 0xff0; @@ -280,26 +263,21 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed) switch (speed) { case XFER_UDMA_6: - idx = 6; - break; case XFER_UDMA_5: - idx = 5; - break; case XFER_UDMA_4: - idx = 4; - break; case XFER_UDMA_3: - idx = 3; - break; case XFER_UDMA_2: - idx = 2; - break; case XFER_UDMA_1: - idx = 1; - break; case XFER_UDMA_0: - idx = 0; + idx = speed - XFER_UDMA_0; break; + case XFER_PIO_4: + case XFER_PIO_3: + case XFER_PIO_2: + case XFER_PIO_1: + case XFER_PIO_0: + scc_tune_pio(drive, speed - XFER_PIO_0); + return ide_config_drive_speed(drive, speed); default: return 1; } @@ -329,7 +307,7 @@ static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed) * required. * If the drive isn't suitable for DMA or we hit other problems * then we will drop down to PIO and set up PIO appropriately. - * (return 1) + * (return -1) */ static int scc_config_drive_for_dma(ide_drive_t *drive) @@ -338,7 +316,7 @@ static int scc_config_drive_for_dma(ide_drive_t *drive) return 0; if (ide_use_fast_pio(drive)) - scc_tuneproc(drive, 4); + scc_tuneproc(drive, 255); return -1; } @@ -401,6 +379,33 @@ static int scc_ide_dma_end(ide_drive_t * drive) ide_hwif_t *hwif = HWIF(drive); unsigned long intsts_port = hwif->dma_base + 0x014; u32 reg; + int dma_stat, data_loss = 0; + static int retry = 0; + + /* errata A308 workaround: Step5 (check data loss) */ + /* We don't check non ide_disk because it is limited to UDMA4 */ + if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) && + drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) { + reg = in_be32((void __iomem *)intsts_port); + if (!(reg & INTSTS_ACTEINT)) { + printk(KERN_WARNING "%s: operation failed (transfer data loss)\n", + drive->name); + data_loss = 1; + if (retry++) { + struct request *rq = HWGROUP(drive)->rq; + int unit; + /* ERROR_RESET and drive->crc_count are needed + * to reduce DMA transfer mode in retry process. + */ + if (rq) + rq->errors |= ERROR_RESET; + for (unit = 0; unit < MAX_DRIVES; unit++) { + ide_drive_t *drive = &hwif->drives[unit]; + drive->crc_count++; + } + } + } + } while (1) { reg = in_be32((void __iomem *)intsts_port); @@ -469,27 +474,25 @@ static int scc_ide_dma_end(ide_drive_t * drive) break; } - return __ide_dma_end(drive); + dma_stat = __ide_dma_end(drive); + if (data_loss) + dma_stat |= 2; /* emulate DMA error (to retry command) */ + return dma_stat; } /* returns 1 if dma irq issued, 0 otherwise */ static int scc_dma_test_irq(ide_drive_t *drive) { - ide_hwif_t *hwif = HWIF(drive); - u8 dma_stat = hwif->INB(hwif->dma_status); + ide_hwif_t *hwif = HWIF(drive); + u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014); - /* return 1 if INTR asserted */ - if ((dma_stat & 4) == 4) + /* SCC errata A252,A308 workaround: Step4 */ + if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) && + (int_stat & INTSTS_INTRQ)) return 1; - /* Workaround for PTERADD: emulate DMA_INTR when - * - IDE_STATUS[ERR] = 1 - * - INT_STATUS[INTRQ] = 1 - * - DMA_STATUS[IORACTA] = 1 - */ - if (in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT && - in_be32((void __iomem *)(hwif->dma_base + 0x014)) & INTSTS_INTRQ && - dma_stat & 1) + /* SCC errata A308 workaround: Step5 (polling IOIRQS) */ + if (int_stat & INTSTS_IOIRQS) return 1; if (!drive->waiting_for_dma) @@ -498,6 +501,21 @@ static int scc_dma_test_irq(ide_drive_t *drive) return 0; } +static u8 scc_udma_filter(ide_drive_t *drive) +{ + ide_hwif_t *hwif = drive->hwif; + u8 mask = hwif->ultra_mask; + + /* errata A308 workaround: limit non ide_disk drive to UDMA4 */ + if ((drive->media != ide_disk) && (mask & 0xE0)) { + printk(KERN_INFO "%s: limit %s to UDMA4\n", + SCC_PATA_NAME, drive->name); + mask = 0x1F; + } + + return mask; +} + /** * setup_mmio_scc - map CTRL/BMID region * @dev: PCI device we are configuring @@ -511,8 +529,8 @@ static int setup_mmio_scc (struct pci_dev *dev, const char *name) unsigned long dma_base = pci_resource_start(dev, 1); unsigned long ctl_size = pci_resource_len(dev, 0); unsigned long dma_size = pci_resource_len(dev, 1); - void *ctl_addr; - void *dma_addr; + void __iomem *ctl_addr; + void __iomem *dma_addr; int i; for (i = 0; i < MAX_HWIFS; i++) { @@ -702,6 +720,7 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif) hwif->tuneproc = scc_tuneproc; hwif->ide_dma_check = scc_config_drive_for_dma; hwif->ide_dma_test_irq = scc_dma_test_irq; + hwif->udma_filter = scc_udma_filter; hwif->drives[0].autotune = IDE_TUNE_AUTO; hwif->drives[1].autotune = IDE_TUNE_AUTO; @@ -716,7 +735,7 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif) hwif->atapi_dma = 1; /* we support 80c cable only. */ - hwif->udma_four = 1; + hwif->cbl = ATA_CBL_PATA80; hwif->autodma = 0; if (!noautodma) @@ -731,9 +750,10 @@ static void __devinit init_hwif_scc(ide_hwif_t *hwif) .init_setup = init_setup_scc, \ .init_iops = init_iops_scc, \ .init_hwif = init_hwif_scc, \ - .channels = 1, \ .autodma = AUTODMA, \ .bootable = ON_BOARD, \ + .host_flags = IDE_HFLAG_SINGLE, \ + .pio_mask = ATA_PIO4, \ } static ide_pci_device_t scc_chipsets[] __devinitdata = {