X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Fpowerpc%2Fboot%2Fdts%2Fmpc8541cds.dts;h=fa8d9aaad157974645ac5988a9ce4d1fcc632217;hb=f9f7dd222364a6428d2ad99a515935dd1dd89d18;hp=070206fffe88c0f7bc9b637e5439c0a026e4561d;hpb=dcb76f88683618ed6ef0df66643dba1285881ee5;p=linux-2.6 diff --git a/arch/powerpc/boot/dts/mpc8541cds.dts b/arch/powerpc/boot/dts/mpc8541cds.dts index 070206fffe..fa8d9aaad1 100644 --- a/arch/powerpc/boot/dts/mpc8541cds.dts +++ b/arch/powerpc/boot/dts/mpc8541cds.dts @@ -16,6 +16,15 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + pci1 = &pci1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -30,7 +39,6 @@ timebase-frequency = <0>; // 33 MHz, from uboot bus-frequency = <0>; // 166 MHz clock-frequency = <0>; // 825 MHz, from uboot - 32-bit; }; }; @@ -42,10 +50,9 @@ soc8541@e0000000 { #address-cells = <1>; #size-cells = <1>; - #interrupt-cells = <2>; device_type = "soc"; ranges = <0 e0000000 00100000>; - reg = ; // CCSRBAR 1M + reg = ; // CCSRBAR 1M bus-frequency = <0>; memory-controller@2000 { @@ -65,7 +72,9 @@ }; i2c@3000 { - device_type = "i2c"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; compatible = "fsl-i2c"; reg = <3000 100>; interrupts = <2b 2>; @@ -76,9 +85,9 @@ mdio@24520 { #address-cells = <1>; #size-cells = <0>; - device_type = "mdio"; - compatible = "gianfar"; + compatible = "fsl,gianfar-mdio"; reg = <24520 20>; + phy0: ethernet-phy@0 { interrupt-parent = <&mpic>; interrupts = <5 1>; @@ -93,9 +102,8 @@ }; }; - ethernet@24000 { - #address-cells = <1>; - #size-cells = <0>; + enet0: ethernet@24000 { + cell-index = <0>; device_type = "network"; model = "TSEC"; compatible = "gianfar"; @@ -106,9 +114,8 @@ phy-handle = <&phy0>; }; - ethernet@25000 { - #address-cells = <1>; - #size-cells = <0>; + enet1: ethernet@25000 { + cell-index = <1>; device_type = "network"; model = "TSEC"; compatible = "gianfar"; @@ -119,7 +126,8 @@ phy-handle = <&phy1>; }; - serial@4500 { + serial0: serial@4500 { + cell-index = <0>; device_type = "serial"; compatible = "ns16550"; reg = <4500 100>; // reg base, size @@ -128,7 +136,8 @@ interrupt-parent = <&mpic>; }; - serial@4600 { + serial1: serial@4600 { + cell-index = <1>; device_type = "serial"; compatible = "ns16550"; reg = <4600 100>; // reg base, size @@ -137,113 +146,147 @@ interrupt-parent = <&mpic>; }; - pci1: pci@8000 { - interrupt-map-mask = <1f800 0 0 7>; - interrupt-map = < - - /* IDSEL 0x10 */ - 08000 0 0 1 &mpic 0 1 - 08000 0 0 2 &mpic 1 1 - 08000 0 0 3 &mpic 2 1 - 08000 0 0 4 &mpic 3 1 - - /* IDSEL 0x11 */ - 08800 0 0 1 &mpic 0 1 - 08800 0 0 2 &mpic 1 1 - 08800 0 0 3 &mpic 2 1 - 08800 0 0 4 &mpic 3 1 - - /* IDSEL 0x12 (Slot 1) */ - 09000 0 0 1 &mpic 0 1 - 09000 0 0 2 &mpic 1 1 - 09000 0 0 3 &mpic 2 1 - 09000 0 0 4 &mpic 3 1 - - /* IDSEL 0x13 (Slot 2) */ - 09800 0 0 1 &mpic 1 1 - 09800 0 0 2 &mpic 2 1 - 09800 0 0 3 &mpic 3 1 - 09800 0 0 4 &mpic 0 1 - - /* IDSEL 0x14 (Slot 3) */ - 0a000 0 0 1 &mpic 2 1 - 0a000 0 0 2 &mpic 3 1 - 0a000 0 0 3 &mpic 0 1 - 0a000 0 0 4 &mpic 1 1 - - /* IDSEL 0x15 (Slot 4) */ - 0a800 0 0 1 &mpic 3 1 - 0a800 0 0 2 &mpic 0 1 - 0a800 0 0 3 &mpic 1 1 - 0a800 0 0 4 &mpic 2 1 - - /* Bus 1 (Tundra Bridge) */ - /* IDSEL 0x12 (ISA bridge) */ - 19000 0 0 1 &mpic 0 1 - 19000 0 0 2 &mpic 1 1 - 19000 0 0 3 &mpic 2 1 - 19000 0 0 4 &mpic 3 1>; - interrupt-parent = <&mpic>; - interrupts = <18 2>; - bus-range = <0 0>; - ranges = <02000000 0 80000000 80000000 0 20000000 - 01000000 0 00000000 e2000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <8000 1000>; - compatible = "85xx"; - device_type = "pci"; - - i8259@19000 { - clock-frequency = <0>; + mpic: pic@40000 { + clock-frequency = <0>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <40000 40000>; + compatible = "chrp,open-pic"; + device_type = "open-pic"; + big-endian; + }; + + cpm@919c0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; + reg = <919c0 30>; + ranges; + + muram@80000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 80000 10000>; + + data@0 { + compatible = "fsl,cpm-muram-data"; + reg = <0 2000 9000 1000>; + }; + }; + + brg@919f0 { + compatible = "fsl,mpc8541-brg", + "fsl,cpm2-brg", + "fsl,cpm-brg"; + reg = <919f0 10 915f0 10>; + }; + + cpmpic: pic@90c00 { interrupt-controller; - device_type = "interrupt-controller"; - reg = <19000 0 0 0 1>; #address-cells = <0>; #interrupt-cells = <2>; - built-in; - compatible = "chrp,iic"; - big-endian; - interrupts = <1>; - interrupt-parent = <&pci1>; + interrupts = <2e 2>; + interrupt-parent = <&mpic>; + reg = <90c00 80>; + compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; }; }; + }; - pci@9000 { - interrupt-map-mask = ; - interrupt-map = < + pci0: pci@e0008000 { + cell-index = <0>; + interrupt-map-mask = <1f800 0 0 7>; + interrupt-map = < - /* IDSEL 0x15 */ - a800 0 0 1 &mpic b 1 - a800 0 0 2 &mpic b 1 - a800 0 0 3 &mpic b 1 - a800 0 0 4 &mpic b 1>; - interrupt-parent = <&mpic>; - interrupts = <19 2>; - bus-range = <0 0>; - ranges = <02000000 0 a0000000 a0000000 0 20000000 - 01000000 0 00000000 e3000000 0 00100000>; - clock-frequency = <3f940aa>; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - reg = <9000 1000>; - compatible = "85xx"; - device_type = "pci"; - }; + /* IDSEL 0x10 */ + 08000 0 0 1 &mpic 0 1 + 08000 0 0 2 &mpic 1 1 + 08000 0 0 3 &mpic 2 1 + 08000 0 0 4 &mpic 3 1 - mpic: pic@40000 { - clock-frequency = <0>; + /* IDSEL 0x11 */ + 08800 0 0 1 &mpic 0 1 + 08800 0 0 2 &mpic 1 1 + 08800 0 0 3 &mpic 2 1 + 08800 0 0 4 &mpic 3 1 + + /* IDSEL 0x12 (Slot 1) */ + 09000 0 0 1 &mpic 0 1 + 09000 0 0 2 &mpic 1 1 + 09000 0 0 3 &mpic 2 1 + 09000 0 0 4 &mpic 3 1 + + /* IDSEL 0x13 (Slot 2) */ + 09800 0 0 1 &mpic 1 1 + 09800 0 0 2 &mpic 2 1 + 09800 0 0 3 &mpic 3 1 + 09800 0 0 4 &mpic 0 1 + + /* IDSEL 0x14 (Slot 3) */ + 0a000 0 0 1 &mpic 2 1 + 0a000 0 0 2 &mpic 3 1 + 0a000 0 0 3 &mpic 0 1 + 0a000 0 0 4 &mpic 1 1 + + /* IDSEL 0x15 (Slot 4) */ + 0a800 0 0 1 &mpic 3 1 + 0a800 0 0 2 &mpic 0 1 + 0a800 0 0 3 &mpic 1 1 + 0a800 0 0 4 &mpic 2 1 + + /* Bus 1 (Tundra Bridge) */ + /* IDSEL 0x12 (ISA bridge) */ + 19000 0 0 1 &mpic 0 1 + 19000 0 0 2 &mpic 1 1 + 19000 0 0 3 &mpic 2 1 + 19000 0 0 4 &mpic 3 1>; + interrupt-parent = <&mpic>; + interrupts = <18 2>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + + i8259@19000 { interrupt-controller; + device_type = "interrupt-controller"; + reg = <19000 0 0 0 1>; #address-cells = <0>; #interrupt-cells = <2>; - reg = <40000 40000>; - built-in; - compatible = "chrp,open-pic"; - device_type = "open-pic"; - big-endian; + compatible = "chrp,iic"; + interrupts = <1>; + interrupt-parent = <&pci0>; }; }; + + pci1: pci@e0009000 { + cell-index = <1>; + interrupt-map-mask = ; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 &mpic b 1 + a800 0 0 2 &mpic b 1 + a800 0 0 3 &mpic b 1 + a800 0 0 4 &mpic b 1>; + interrupt-parent = <&mpic>; + interrupts = <19 2>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = ; + compatible = "fsl,mpc8540-pci"; + device_type = "pci"; + }; };