X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Fblackfin%2FKconfig;h=9f9de3e95826031eaaf08ba79ab5170bc59ce7c7;hb=8854cb49a249c8df883874e64dfbc25eaa69a6ee;hp=4c5ca9d5e40f74f0083e21b7dd2cc1f0bdf78467;hpb=f768f9d3757be475a20cb5f9d63bda45934150b1;p=linux-2.6 diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 4c5ca9d5e4..9f9de3e958 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig @@ -71,7 +71,7 @@ config GENERIC_CALIBRATE_DELAY config IRQCHIP_DEMUX_GPIO bool - depends on (BF53x || BF561 || BF54x) + depends on (BF52x || BF53x || BF561 || BF54x) default y source "init/Kconfig" @@ -85,6 +85,21 @@ choice prompt "CPU" default BF533 +config BF522 + bool "BF522" + help + BF522 Processor Support. + +config BF525 + bool "BF525" + help + BF525 Processor Support. + +config BF527 + bool "BF527" + help + BF527 Processor Support. + config BF531 bool "BF531" help @@ -144,13 +159,18 @@ endchoice choice prompt "Silicon Rev" + default BF_REV_0_1 if BF527 default BF_REV_0_2 if BF537 default BF_REV_0_3 if BF533 default BF_REV_0_0 if BF549 config BF_REV_0_0 bool "0.0" - depends on (BF549) + depends on (BF549 || BF527) + +config BF_REV_0_1 + bool "0.2" + depends on (BF549 || BF527) config BF_REV_0_2 bool "0.2" @@ -176,6 +196,11 @@ config BF_REV_NONE endchoice +config BF52x + bool + depends on (BF522 || BF525 || BF527) + default y + config BF53x bool depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) @@ -204,6 +229,12 @@ choice configuration to ensure that all the other settings are correct. +config BFIN527_EZKIT + bool "BF527-EZKIT" + depends on (BF522 || BF525 || BF527) + help + BF533-EZKIT-LITE board Support. + config BFIN533_EZKIT bool "BF533-EZKIT" depends on (BF533 || BF532 || BF531) @@ -264,6 +295,12 @@ config PNAV10 help PNAV 1.0 board Support. +config H8606_HVSISTEMAS + bool "HV Sistemas H8606" + depends on (BF532) + help + HV Sistemas H8606 board support. + config GENERIC_BOARD bool "Custom" depends on (BF537 || BF536 \ @@ -286,7 +323,8 @@ config MEM_MT48LC64M4A2FB_7E config MEM_MT48LC16M16A2TG_75 bool depends on (BFIN533_EZKIT || BFIN561_EZKIT \ - || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM) + || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ + || H8606_HVSISTEMAS) default y config MEM_MT48LC32M8A2_75 @@ -299,11 +337,17 @@ config MEM_MT48LC8M32B2B5_7 depends on (BFIN561_BLUETECHNIX_CM) default y +config MEM_MT48LC32M16A2TG_75 + bool + depends on (BFIN527_EZKIT) + default y + config BFIN_SHARED_FLASH_ENET bool depends on (BFIN533_STAMP) default y +source "arch/blackfin/mach-bf527/Kconfig" source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf561/Kconfig" source "arch/blackfin/mach-bf537/Kconfig" @@ -329,7 +373,7 @@ config CLKIN_HZ int "Crystal Frequency in Hz" default "11059200" if BFIN533_STAMP default "27000000" if BFIN533_EZKIT - default "25000000" if BFIN537_STAMP + default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS) default "30000000" if BFIN561_EZKIT default "24576000" if PNAV10 help @@ -362,11 +406,12 @@ config VCO_MULT range 1 64 default "22" if BFIN533_EZKIT default "45" if BFIN533_STAMP - default "20" if BFIN537_STAMP + default "20" if (BFIN537_STAMP || BFIN527_EZKIT) default "22" if BFIN533_BLUETECHNIX_CM default "20" if BFIN537_BLUETECHNIX_CM default "20" if BFIN561_BLUETECHNIX_CM default "20" if BFIN561_EZKIT + default "16" if H8606_HVSISTEMAS help This controls the frequency of the on-chip PLL. This can be between 1 and 64. PLL Frequency = (Crystal Frequency) * (this setting) @@ -398,11 +443,12 @@ config SCLK_DIV range 1 15 default 5 if BFIN533_EZKIT default 5 if BFIN533_STAMP - default 4 if BFIN537_STAMP + default 4 if (BFIN537_STAMP || BFIN527_EZKIT) default 5 if BFIN533_BLUETECHNIX_CM default 4 if BFIN537_BLUETECHNIX_CM default 4 if BFIN561_BLUETECHNIX_CM default 5 if BFIN561_EZKIT + default 3 if H8606_HVSISTEMAS help This sets the frequency of the system clock (including SDRAM or DDR). This can be between 1 and 15 @@ -450,15 +496,19 @@ comment "Memory Setup" config MEM_SIZE int "SDRAM Memory Size in MBytes" default 32 if BFIN533_EZKIT + default 64 if BFIN527_EZKIT default 64 if BFIN537_STAMP default 64 if BFIN561_EZKIT default 128 if BFIN533_STAMP default 64 if PNAV10 + default 32 if H8606_HVSISTEMAS config MEM_ADD_WIDTH int "SDRAM Memory Address Width" default 9 if BFIN533_EZKIT default 9 if BFIN561_EZKIT + default 9 if H8606_HVSISTEMAS + default 10 if BFIN527_EZKIT default 10 if BFIN537_STAMP default 11 if BFIN533_STAMP default 10 if PNAV10 @@ -613,85 +663,86 @@ config I_ENTRY_L1 bool "Locate interrupt entry code in L1 Memory" default y help - If enabled interrupt entry code (STORE/RESTORE CONTEXT) is linked - into L1 instruction memory.(less latency) + If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked + into L1 instruction memory. (less latency) config EXCPT_IRQ_SYSC_L1 - bool "Locate entire ASM lowlevel excepetion / interrupt - Syscall and CPLB handler code in L1 Memory" + bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" default y help - If enabled entire ASM lowlevel exception and interrupt entry code (STORE/RESTORE CONTEXT) is linked - into L1 instruction memory.(less latency) + If enabled, the entire ASM lowlevel exception and interrupt entry code + (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. + (less latency) config DO_IRQ_L1 bool "Locate frequently called do_irq dispatcher function in L1 Memory" default y help - If enabled frequently called do_irq dispatcher function is linked - into L1 instruction memory.(less latency) + If enabled, the frequently called do_irq dispatcher function is linked + into L1 instruction memory. (less latency) config CORE_TIMER_IRQ_L1 bool "Locate frequently called timer_interrupt() function in L1 Memory" default y help - If enabled frequently called timer_interrupt() function is linked - into L1 instruction memory.(less latency) + If enabled, the frequently called timer_interrupt() function is linked + into L1 instruction memory. (less latency) config IDLE_L1 bool "Locate frequently idle function in L1 Memory" default y help - If enabled frequently called idle function is linked - into L1 instruction memory.(less latency) + If enabled, the frequently called idle function is linked + into L1 instruction memory. (less latency) config SCHEDULE_L1 bool "Locate kernel schedule function in L1 Memory" default y help - If enabled frequently called kernel schedule is linked - into L1 instruction memory.(less latency) + If enabled, the frequently called kernel schedule is linked + into L1 instruction memory. (less latency) config ARITHMETIC_OPS_L1 bool "Locate kernel owned arithmetic functions in L1 Memory" default y help - If enabled arithmetic functions are linked - into L1 instruction memory.(less latency) + If enabled, arithmetic functions are linked + into L1 instruction memory. (less latency) config ACCESS_OK_L1 bool "Locate access_ok function in L1 Memory" default y help - If enabled access_ok function is linked - into L1 instruction memory.(less latency) + If enabled, the access_ok function is linked + into L1 instruction memory. (less latency) config MEMSET_L1 bool "Locate memset function in L1 Memory" default y help - If enabled memset function is linked - into L1 instruction memory.(less latency) + If enabled, the memset function is linked + into L1 instruction memory. (less latency) config MEMCPY_L1 bool "Locate memcpy function in L1 Memory" default y help - If enabled memcpy function is linked - into L1 instruction memory.(less latency) + If enabled, the memcpy function is linked + into L1 instruction memory. (less latency) config SYS_BFIN_SPINLOCK_L1 bool "Locate sys_bfin_spinlock function in L1 Memory" default y help - If enabled sys_bfin_spinlock function is linked - into L1 instruction memory.(less latency) + If enabled, sys_bfin_spinlock function is linked + into L1 instruction memory. (less latency) config IP_CHECKSUM_L1 bool "Locate IP Checksum function in L1 Memory" default n help - If enabled IP Checksum function is linked - into L1 instruction memory.(less latency) + If enabled, the IP Checksum function is linked + into L1 instruction memory. (less latency) config CACHELINE_ALIGNED_L1 bool "Locate cacheline_aligned data to L1 Data Memory" @@ -699,24 +750,24 @@ config CACHELINE_ALIGNED_L1 default n if BF54x depends on !BF531 help - If enabled cacheline_anligned data is linked - into L1 data memory.(less latency) + If enabled, cacheline_anligned data is linked + into L1 data memory. (less latency) config SYSCALL_TAB_L1 bool "Locate Syscall Table L1 Data Memory" default n depends on !BF531 help - If enabled the Syscall LUT is linked - into L1 data memory.(less latency) + If enabled, the Syscall LUT is linked + into L1 data memory. (less latency) config CPLB_SWITCH_TAB_L1 bool "Locate CPLB Switch Tables L1 Data Memory" default n depends on !BF531 help - If enabled the CPLB Switch Tables are linked - into L1 data memory.(less latency) + If enabled, the CPLB Switch Tables are linked + into L1 data memory. (less latency) endmenu @@ -748,9 +799,19 @@ config LARGE_ALLOCS a lot of RAM, and you need to able to allocate very large contiguous chunks. If unsure, say N. +config BFIN_GPTIMERS + tristate "Enable Blackfin General Purpose Timers API" + default n + help + Enable support for the General Purpose Timers API. If you + are unsure, say N. + + To compile this driver as a module, choose M here: the module + will be called gptimers.ko. + config BFIN_DMA_5XX bool "Enable DMA Support" - depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x) + depends on (BF52x || BF53x || BF561 || BF54x) default y help DMA driver for BF5xx. @@ -1029,13 +1090,13 @@ config DEBUG_HWERR from. config DEBUG_ICACHE_CHECK - bool "Check Instruction cache coherancy" + bool "Check Instruction cache coherency" depends on DEBUG_KERNEL depends on DEBUG_HWERR help - Say Y here if you are getting wierd unexplained errors. This will - ensure that icache is what SDRAM says it should be, by doing a - byte wise comparision between SDRAM and instruction cache. This + Say Y here if you are getting weird unexplained errors. This will + ensure that icache is what SDRAM says it should be by doing a + byte wise comparison between SDRAM and instruction cache. This also relocates the irq_panic() function to L1 memory, (which is un-cached).