X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-pxa%2Fpxa3xx.c;h=dde355e88fa1574d3760a778a4cb7bf8297d166a;hb=b0d19a378a409373244088511e889957645f2a44;hp=5cbf057a1b32f4ce2c6f05d137efad8f086d0c74;hpb=f4798748dee00c807a63f5518f08b3df161e0f6d;p=linux-2.6 diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 5cbf057a1b..dde355e88f 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ #define RO_CLK 60000000 #define ACCR_D0CS (1 << 26) +#define ACCR_PCCE (1 << 11) /* crystal frequency to static memory controller multiplier (SMCFS) */ static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; @@ -107,6 +109,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void) return (clk / 10000); } +/* + * Return the current AC97 clock frequency. + */ +static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk) +{ + unsigned long rate = 312000000; + unsigned long ac97_div; + + ac97_div = AC97_DIV; + + /* This may loose precision for some rates but won't for the + * standard 24.576MHz. + */ + rate /= (ac97_div >> 12) & 0x7fff; + rate *= (ac97_div & 0xfff); + + return rate; +} + /* * Return the current HSIO bus clock frequency */ @@ -127,28 +148,20 @@ static void clk_pxa3xx_cken_enable(struct clk *clk) { unsigned long mask = 1ul << (clk->cken & 0x1f); - local_irq_disable(); - if (clk->cken < 32) CKENA |= mask; else CKENB |= mask; - - local_irq_enable(); } static void clk_pxa3xx_cken_disable(struct clk *clk) { unsigned long mask = 1ul << (clk->cken & 0x1f); - local_irq_disable(); - if (clk->cken < 32) CKENA &= ~mask; else CKENB &= ~mask; - - local_irq_enable(); } static const struct clkops clk_pxa3xx_cken_ops = { @@ -162,6 +175,27 @@ static const struct clkops clk_pxa3xx_hsio_ops = { .getrate = clk_pxa3xx_hsio_getrate, }; +static const struct clkops clk_pxa3xx_ac97_ops = { + .enable = clk_pxa3xx_cken_enable, + .disable = clk_pxa3xx_cken_disable, + .getrate = clk_pxa3xx_ac97_getrate, +}; + +static void clk_pout_enable(struct clk *clk) +{ + OSCC |= OSCC_PEN; +} + +static void clk_pout_disable(struct clk *clk) +{ + OSCC &= ~OSCC_PEN; +} + +static const struct clkops clk_pout_ops = { + .enable = clk_pout_enable, + .disable = clk_pout_disable, +}; + #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \ { \ .name = _name, \ @@ -181,8 +215,16 @@ static const struct clkops clk_pxa3xx_hsio_ops = { } static struct clk pxa3xx_clks[] = { - PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), - PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), + { + .name = "CLK_POUT", + .ops = &clk_pout_ops, + .rate = 13000000, + .delay = 70, + }, + + PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev), + PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL), + PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL), PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev), PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev), @@ -191,6 +233,7 @@ static struct clk pxa3xx_clks[] = { PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev), PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev), PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev), + PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev), PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev), PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev), @@ -203,7 +246,6 @@ static struct clk pxa3xx_clks[] = { }; #ifdef CONFIG_PM -#define SLEEP_SAVE_SIZE 4 #define ISRAM_START 0x5c000000 #define ISRAM_SIZE SZ_256K @@ -211,25 +253,29 @@ static struct clk pxa3xx_clks[] = { static void __iomem *sram; static unsigned long wakeup_src; -static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) -{ - pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB); +#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x +#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] - if (CKENA & (1 << CKEN_USBH)) { - printk(KERN_ERR "PM: USB host clock not stopped?\n"); - CKENA &= ~(1 << CKEN_USBH); - } -// CKENA |= 1 << (CKEN_ISC & 31); +enum { SLEEP_SAVE_START = 0, + SLEEP_SAVE_CKENA, + SLEEP_SAVE_CKENB, + SLEEP_SAVE_ACCR, - /* - * Low power modes require the HSIO2 clock to be enabled. - */ - CKENB |= 1 << (CKEN_HSIO2 & 31); + SLEEP_SAVE_SIZE, +}; + +static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) +{ + SAVE(CKENA); + SAVE(CKENB); + SAVE(ACCR); } static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save) { - CKENB &= ~(1 << (CKEN_HSIO2 & 31)); + RESTORE(ACCR); + RESTORE(CKENA); + RESTORE(CKENB); } /* @@ -261,8 +307,46 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode) AD2D0ER = 0; AD2D1ER = 0; +} + +/* + * NOTE: currently, the OBM (OEM Boot Module) binary comes along with + * PXA3xx development kits assumes that the resuming process continues + * with the address stored within the first 4 bytes of SDRAM. The PSPR + * register is used privately by BootROM and OBM, and _must_ be set to + * 0x5c014000 for the moment. + */ +static void pxa3xx_cpu_pm_suspend(void) +{ + volatile unsigned long *p = (volatile void *)0xc0000000; + unsigned long saved_data = *p; + + extern void pxa3xx_cpu_suspend(void); + extern void pxa3xx_cpu_resume(void); + + /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ + CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); + CKENB |= 1 << (CKEN_HSIO2 & 0x1f); + + /* clear and setup wakeup source */ + AD3SR = ~0; + AD3ER = wakeup_src; + ASCR = ASCR; + ARSR = ARSR; + + PCFR |= (1u << 13); /* L1_DIS */ + PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ + + PSPR = 0x5c014000; - printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR); + /* overwrite with the resume address */ + *p = virt_to_phys(pxa3xx_cpu_resume); + + pxa3xx_cpu_suspend(); + + *p = saved_data; + + AD3ER = 0; } static void pxa3xx_cpu_pm_enter(suspend_state_t state) @@ -270,8 +354,10 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state) /* * Don't sleep if no wakeup sources are defined */ - if (wakeup_src == 0) + if (wakeup_src == 0) { + printk(KERN_ERR "Not suspending: no wakeup sources\n"); return; + } switch (state) { case PM_SUSPEND_STANDBY: @@ -279,6 +365,7 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state) break; case PM_SUSPEND_MEM: + pxa3xx_cpu_pm_suspend(); break; } } @@ -410,15 +497,9 @@ static int pxa3xx_set_wake(unsigned int irq, unsigned int on) return 0; } - -static void pxa3xx_init_irq_pm(void) -{ - pxa_init_irq_set_wake(pxa3xx_set_wake); -} - #else static inline void pxa3xx_init_pm(void) {} -static inline void pxa3xx_init_irq_pm(void) {} +#define pxa3xx_set_wake NULL #endif void __init pxa3xx_init_irq(void) @@ -429,10 +510,8 @@ void __init pxa3xx_init_irq(void) value |= (1 << 6); __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); - pxa_init_irq_low(); - pxa_init_irq_high(); - pxa_init_irq_gpio(128); - pxa3xx_init_irq_pm(); + pxa_init_irq(56, pxa3xx_set_wake); + pxa_init_gpio(128, NULL); } /* @@ -452,11 +531,29 @@ static struct platform_device *devices[] __initdata = { &pxa3xx_device_ssp4, }; +static struct sys_device pxa3xx_sysdev[] = { + { + .cls = &pxa_irq_sysclass, + }, { + .cls = &pxa3xx_mfp_sysclass, + }, { + .cls = &pxa_gpio_sysclass, + }, +}; + static int __init pxa3xx_init(void) { - int ret = 0; + int i, ret = 0; if (cpu_is_pxa3xx()) { + /* + * clear RDH bit every time after reset + * + * Note: the last 3 bits DxS are write-1-to-clear so carefully + * preserve them here in case they will be referenced later + */ + ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); + clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks)); if ((ret = pxa_init_dma(32))) @@ -464,9 +561,16 @@ static int __init pxa3xx_init(void) pxa3xx_init_pm(); - return platform_add_devices(devices, ARRAY_SIZE(devices)); + for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) { + ret = sysdev_register(&pxa3xx_sysdev[i]); + if (ret) + pr_err("failed to register sysdev[%d]\n", i); + } + + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); } - return 0; + + return ret; } -subsys_initcall(pxa3xx_init); +postcore_initcall(pxa3xx_init);