X-Git-Url: https://err.no/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=arch%2Farm%2Fmach-pxa%2Fpxa3xx.c;h=dde355e88fa1574d3760a778a4cb7bf8297d166a;hb=548453fd107f789f5f1bc2dc13cc432ceb3b5efd;hp=e47e67c11afe65dfbc10f234c1dbfe8dc636cf32;hpb=5531d28504461c4e96c6fbd80655a2bfd6481583;p=linux-2.6

diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index e47e67c11a..dde355e88f 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -109,6 +109,25 @@ unsigned int pxa3xx_get_memclk_frequency_10khz(void)
 	return (clk / 10000);
 }
 
+/*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+	unsigned long rate = 312000000;
+	unsigned long ac97_div;
+
+	ac97_div = AC97_DIV;
+
+	/* This may loose precision for some rates but won't for the
+	 * standard 24.576MHz.
+	 */
+	rate /= (ac97_div >> 12) & 0x7fff;
+	rate *= (ac97_div & 0xfff);
+
+	return rate;
+}
+
 /*
  * Return the current HSIO bus clock frequency
  */
@@ -129,28 +148,20 @@ static void clk_pxa3xx_cken_enable(struct clk *clk)
 {
 	unsigned long mask = 1ul << (clk->cken & 0x1f);
 
-	local_irq_disable();
-
 	if (clk->cken < 32)
 		CKENA |= mask;
 	else
 		CKENB |= mask;
-
-	local_irq_enable();
 }
 
 static void clk_pxa3xx_cken_disable(struct clk *clk)
 {
 	unsigned long mask = 1ul << (clk->cken & 0x1f);
 
-	local_irq_disable();
-
 	if (clk->cken < 32)
 		CKENA &= ~mask;
 	else
 		CKENB &= ~mask;
-
-	local_irq_enable();
 }
 
 static const struct clkops clk_pxa3xx_cken_ops = {
@@ -164,6 +175,27 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
 	.getrate	= clk_pxa3xx_hsio_getrate,
 };
 
+static const struct clkops clk_pxa3xx_ac97_ops = {
+	.enable		= clk_pxa3xx_cken_enable,
+	.disable	= clk_pxa3xx_cken_disable,
+	.getrate	= clk_pxa3xx_ac97_getrate,
+};
+
+static void clk_pout_enable(struct clk *clk)
+{
+	OSCC |= OSCC_PEN;
+}
+
+static void clk_pout_disable(struct clk *clk)
+{
+	OSCC &= ~OSCC_PEN;
+}
+
+static const struct clkops clk_pout_ops = {
+	.enable		= clk_pout_enable,
+	.disable	= clk_pout_disable,
+};
+
 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev)	\
 	{						\
 		.name	= _name,			\
@@ -183,8 +215,16 @@ static const struct clkops clk_pxa3xx_hsio_ops = {
 	}
 
 static struct clk pxa3xx_clks[] = {
-	PXA3xx_CK("LCDCLK", LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
-	PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+	{
+		.name           = "CLK_POUT",
+		.ops            = &clk_pout_ops,
+		.rate           = 13000000,
+		.delay          = 70,
+	},
+
+	PXA3xx_CK("LCDCLK",  LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
+	PXA3xx_CK("CAMCLK",  CAMERA, &clk_pxa3xx_hsio_ops, NULL),
+	PXA3xx_CK("AC97CLK", AC97,   &clk_pxa3xx_ac97_ops, NULL),
 
 	PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
 	PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
@@ -193,6 +233,7 @@ static struct clk pxa3xx_clks[] = {
 	PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
 	PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
 	PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
+	PXA3xx_CKEN("KBDCLK", KEYPAD,  32768, 0, &pxa27x_device_keypad.dev),
 
 	PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
 	PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
@@ -266,8 +307,6 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode)
 
 	AD2D0ER = 0;
 	AD2D1ER = 0;
-
-	printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
 }
 
 /*
@@ -315,8 +354,10 @@ static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 	/*
 	 * Don't sleep if no wakeup sources are defined
 	 */
-	if (wakeup_src == 0)
+	if (wakeup_src == 0) {
+		printk(KERN_ERR "Not suspending: no wakeup sources\n");
 		return;
+	}
 
 	switch (state) {
 	case PM_SUSPEND_STANDBY:
@@ -456,15 +497,9 @@ static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 
 	return 0;
 }
-
-static void pxa3xx_init_irq_pm(void)
-{
-	pxa_init_irq_set_wake(pxa3xx_set_wake);
-}
-
 #else
 static inline void pxa3xx_init_pm(void) {}
-static inline void pxa3xx_init_irq_pm(void) {}
+#define pxa3xx_set_wake	NULL
 #endif
 
 void __init pxa3xx_init_irq(void)
@@ -475,10 +510,8 @@ void __init pxa3xx_init_irq(void)
 	value |= (1 << 6);
 	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
-	pxa_init_irq_low();
-	pxa_init_irq_high();
-	pxa_init_irq_gpio(128);
-	pxa3xx_init_irq_pm();
+	pxa_init_irq(56, pxa3xx_set_wake);
+	pxa_init_gpio(128, NULL);
 }
 
 /*
@@ -500,11 +533,9 @@ static struct platform_device *devices[] __initdata = {
 
 static struct sys_device pxa3xx_sysdev[] = {
 	{
-		.id	= 0,
 		.cls	= &pxa_irq_sysclass,
 	}, {
-		.id	= 1,
-		.cls	= &pxa_irq_sysclass,
+		.cls	= &pxa3xx_mfp_sysclass,
 	}, {
 		.cls	= &pxa_gpio_sysclass,
 	},
@@ -515,6 +546,14 @@ static int __init pxa3xx_init(void)
 	int i, ret = 0;
 
 	if (cpu_is_pxa3xx()) {
+		/*
+		 * clear RDH bit every time after reset
+		 *
+		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
+		 * preserve them here in case they will be referenced later
+		 */
+		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
+
 		clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
 
 		if ((ret = pxa_init_dma(32)))
@@ -534,4 +573,4 @@ static int __init pxa3xx_init(void)
 	return ret;
 }
 
-subsys_initcall(pxa3xx_init);
+postcore_initcall(pxa3xx_init);