if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
return;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/100);
+ msleep(10);
} while (time_after_eq(end_time, jiffies));
snd_printk("CS46xx secondary codec dont respond!\n");
err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
return err;
}
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(HZ/100);
+ msleep(10);
}
snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
return -ENXIO;
/*
* Wait until the PLL has stabilized.
*/
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(HZ/10); /* 100ms */
+ msleep(100);
/*
* Turn on clocking of the core so that we can setup the serial ports.
*/
if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
goto ok1;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout((HZ+99)/100);
+ msleep(10);
}
*/
if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
goto ok2;
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout((HZ+99)/100);
+ msleep(10);
}
#ifndef CONFIG_SND_CS46XX_NEW_DSP