static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
-static struct pci_device_id snd_cs4281_ids[] = {
+static struct pci_device_id snd_cs4281_ids[] __devinitdata = {
{ 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
{ 0, }
};
snd_cs4281_pokeBA0(chip, regL, volL);
change = 1;
}
- if (ucontrol->value.integer.value[0] != volL) {
+ if (ucontrol->value.integer.value[1] != volR) {
volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
snd_cs4281_pokeBA0(chip, regR, volR);
change = 1;
static int snd_cs4281_chip_init(struct cs4281 *chip)
{
unsigned int tmp;
- int timeout;
+ unsigned long end_time;
int retry_count = 2;
/* Having EPPMC.FPDN=1 prevent proper chip initialisation */
/*
* Wait for the DLL ready signal from the clock logic.
*/
- timeout = 100;
+ end_time = jiffies + HZ;
do {
/*
* Read the AC97 status register to see if we've seen a CODEC
*/
if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
goto __ok0;
- msleep(1);
- } while (timeout-- > 0);
+ schedule_timeout_uninterruptible(1);
+ } while (time_after_eq(end_time, jiffies));
snd_printk(KERN_ERR "DLLRDY not seen\n");
return -EIO;
/*
* Wait for the codec ready signal from the AC97 codec.
*/
- timeout = 100;
+ end_time = jiffies + HZ;
do {
/*
* Read the AC97 status register to see if we've seen a CODEC
*/
if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
goto __ok1;
- msleep(1);
- } while (timeout-- > 0);
+ schedule_timeout_uninterruptible(1);
+ } while (time_after_eq(end_time, jiffies));
snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
return -EIO;
__ok1:
if (chip->dual_codec) {
- timeout = 100;
+ end_time = jiffies + HZ;
do {
if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
goto __codec2_ok;
- msleep(1);
- } while (timeout-- > 0);
+ schedule_timeout_uninterruptible(1);
+ } while (time_after_eq(end_time, jiffies));
snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
chip->dual_codec = 0;
__codec2_ok: ;
* the codec is pumping ADC data across the AC-link.
*/
- timeout = 100;
+ end_time = jiffies + HZ;
do {
/*
* Read the input slot valid register and see if input slots 3
*/
if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
goto __ok2;
- msleep(1);
- } while (timeout-- > 0);
+ schedule_timeout_uninterruptible(1);
+ } while (time_after_eq(end_time, jiffies));
if (--retry_count > 0)
goto __retry;