};
/*
- * Contains all information which are necessary for DMA operations
+ * Contains DMA mapped address information
*/
struct i2o_dma {
void *virt;
dma_addr_t phys;
- u32 len;
+ size_t len;
+};
+
+/*
+ * Contains IO mapped address information
+ */
+struct i2o_io {
+ void __iomem *virt;
+ unsigned long phys;
+ unsigned long len;
};
/*
struct pci_dev *pdev; /* PCI device */
- unsigned int short_req:1; /* use small block sizes */
+ unsigned int promise:1; /* Promise controller */
+ unsigned int adaptec:1; /* DPT / Adaptec controller */
+ unsigned int raptor:1; /* split bar */
unsigned int no_quiesce:1; /* dont quiesce before reset */
- unsigned int raptor:1; /* split bar */
- unsigned int promise:1; /* Promise controller */
+ unsigned int short_req:1; /* use small block sizes */
+ unsigned int limit_sectors:1; /* limit number of sectors / request */
+ unsigned int pae_support:1; /* controller has 64-bit SGL support */
struct list_head devices; /* list of I2O devices */
struct list_head list; /* Controller list */
/* Dynamic LCT related data */
- struct i2o_dma status; /* status of IOP */
+ struct i2o_dma status; /* IOP status block */
struct i2o_dma hrt; /* HW Resource Table */
i2o_lct *lct; /* Logical Config Table */
struct semaphore lct_lock; /* Lock for LCT updates */
struct i2o_dma status_block; /* IOP status block */
- struct i2o_dma base; /* controller messaging unit */
- struct i2o_dma in_queue; /* inbound message queue Host->IOP */
+ struct i2o_io base; /* controller messaging unit */
+ struct i2o_io in_queue; /* inbound message queue Host->IOP */
struct i2o_dma out_queue; /* outbound message queue IOP->Host */
- unsigned int battery:1; /* Has a battery backup */
+ unsigned int battery:1; /* Has a battery backup */
unsigned int io_alloc:1; /* An I/O resource was allocated */
unsigned int mem_alloc:1; /* A memory resource was allocated */
struct resource mem_resource; /* Mem resource allocated to the IOP */
struct device device;
+ struct class_device classdev; /* I2O controller class */
struct i2o_device *exec; /* Executive */
#if BITS_PER_LONG == 64
spinlock_t context_list_lock; /* lock for context_list */
extern struct list_head i2o_controllers;
/* Message functions */
-static inline u32 i2o_msg_get(struct i2o_controller *, struct i2o_message __iomem **);
-extern u32 i2o_msg_get_wait(struct i2o_controller *, struct i2o_message __iomem **,
- int);
+static inline u32 i2o_msg_get(struct i2o_controller *,
+ struct i2o_message __iomem **);
+extern u32 i2o_msg_get_wait(struct i2o_controller *,
+ struct i2o_message __iomem **, int);
static inline void i2o_msg_post(struct i2o_controller *, u32);
static inline int i2o_msg_post_wait(struct i2o_controller *, u32,
unsigned long);
* available returns I2O_QUEUE_EMPTY and msg is leaved untouched.
*/
static inline u32 i2o_msg_get(struct i2o_controller *c,
- struct i2o_message __iomem **msg)
+ struct i2o_message __iomem ** msg)
{
u32 m = readl(c->in_port);
- if (m != I2O_QUEUE_EMPTY) {
+ if (m != I2O_QUEUE_EMPTY)
*msg = c->in_queue.virt + m;
- rmb();
- }
return m;
};
*/
static inline void i2o_msg_post(struct i2o_controller *c, u32 m)
{
- wmb();
writel(m, c->in_port);
};
* work for sender side messages as they are ioremap objects
* provided by the I2O controller.
*/
-static inline struct i2o_message __iomem *i2o_msg_out_to_virt(struct
- i2o_controller *c,
- u32 m)
+static inline struct i2o_message *i2o_msg_out_to_virt(struct i2o_controller *c,
+ u32 m)
{
- if (unlikely
- (m < c->out_queue.phys
- || m >= c->out_queue.phys + c->out_queue.len))
- return NULL;
+ BUG_ON(m < c->out_queue.phys
+ || m >= c->out_queue.phys + c->out_queue.len);
return c->out_queue.virt + (m - c->out_queue.phys);
};
* work for receive side messages as they are kmalloc objects
* in a different pool.
*/
-static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct i2o_controller *c,
- u32 m)
+static inline struct i2o_message __iomem *i2o_msg_in_to_virt(struct
+ i2o_controller *c,
+ u32 m)
{
return c->in_queue.virt + m;
};
-/**
- * i2o_dma_alloc - Allocate DMA memory
- * @dev: struct device pointer to the PCI device of the I2O controller
- * @addr: i2o_dma struct which should get the DMA buffer
- * @len: length of the new DMA memory
- * @gfp_mask: GFP mask
- *
- * Allocate a coherent DMA memory and write the pointers into addr.
- *
- * Returns 0 on success or -ENOMEM on failure.
- */
-static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
- size_t len, unsigned int gfp_mask)
-{
- addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
- if (!addr->virt)
- return -ENOMEM;
-
- memset(addr->virt, 0, len);
- addr->len = len;
-
- return 0;
-};
-
-/**
- * i2o_dma_free - Free DMA memory
- * @dev: struct device pointer to the PCI device of the I2O controller
- * @addr: i2o_dma struct which contains the DMA buffer
- *
- * Free a coherent DMA memory and set virtual address of addr to NULL.
- */
-static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
-{
- if (addr->virt) {
- if (addr->phys)
- dma_free_coherent(dev, addr->len, addr->virt,
- addr->phys);
- else
- kfree(addr->virt);
- addr->virt = NULL;
- }
-};
-
/*
* Endian handling wrapped into the macro - keeps the core code
* cleaner.
#define I2O_CMD_BLOCK_MEJECT 0x43
#define I2O_CMD_BLOCK_POWER 0x70
-#define I2O_PRIVATE_MSG 0xFF
+#define I2O_CMD_PRIVATE 0xFF
/* Command status values */
#define SGL_OFFSET_8 (0x0080 | I2OVERSION)
#define SGL_OFFSET_9 (0x0090 | I2OVERSION)
#define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
-
-#define TRL_OFFSET_5 (0x0050 | I2OVERSION)
-#define TRL_OFFSET_6 (0x0060 | I2OVERSION)
+#define SGL_OFFSET_11 (0x00B0 | I2OVERSION)
+#define SGL_OFFSET_12 (0x00C0 | I2OVERSION)
+#define SGL_OFFSET(x) (((x)<<4) | I2OVERSION)
/* Transaction Reply Lists (TRL) Control Word structure */
#define TRL_SINGLE_FIXED_LENGTH 0x00
#define ELEVEN_WORD_MSG_SIZE 0x000B0000
#define I2O_MESSAGE_SIZE(x) ((x)<<16)
-/* Special TID Assignments */
-
+/* special TID assignments */
#define ADAPTER_TID 0
#define HOST_TID 1
-#define MSG_FRAME_SIZE 128 /* i2o_scsi assumes >= 32 */
-#define REPLY_FRAME_SIZE 17
-#define SG_TABLESIZE 30
-#define NMBR_MSG_FRAMES 128
-
-#define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
+/* outbound queue defines */
+#define I2O_MAX_OUTBOUND_MSG_FRAMES 128
+#define I2O_OUTBOUND_MSG_FRAME_SIZE 128 /* in 32-bit words */
#define I2O_POST_WAIT_OK 0
#define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
#define I2O_HRT_GET_TRIES 3
#define I2O_LCT_GET_TRIES 3
-/* request queue sizes */
+/* defines for max_sectors and max_phys_segments */
#define I2O_MAX_SECTORS 1024
+#define I2O_MAX_SECTORS_LIMITED 256
#define I2O_MAX_PHYS_SEGMENTS MAX_PHYS_SEGMENTS
-#define I2O_REQ_MEMPOOL_SIZE 32
-
#endif /* __KERNEL__ */
#endif /* _I2O_H */
projects / linux-2.6 / blobdiff