/*
* Flush all tlb entries of a page table on all cpus.
*/
-static inline void __tlb_flush_idte(pgd_t *pgd)
+static inline void __tlb_flush_idte(unsigned long asce)
{
asm volatile(
" .insn rrf,0xb98e0000,0,%0,%1,0"
- : : "a" (2048), "a" (__pa(pgd) & PAGE_MASK) : "cc" );
+ : : "a" (2048), "a" (asce) : "cc" );
}
static inline void __tlb_flush_mm(struct mm_struct * mm)
* only ran on the local cpu.
*/
if (MACHINE_HAS_IDTE) {
- pgd_t *shadow_pgd = get_shadow_table(mm->pgd);
-
- if (shadow_pgd)
- __tlb_flush_idte(shadow_pgd);
- __tlb_flush_idte(mm->pgd);
+ if (mm->context.noexec)
+ __tlb_flush_idte((unsigned long)
+ get_shadow_table(mm->pgd) |
+ mm->context.asce_bits);
+ __tlb_flush_idte((unsigned long) mm->pgd |
+ mm->context.asce_bits);
return;
}
preempt_disable();
*/
#define flush_tlb() do { } while (0)
#define flush_tlb_all() do { } while (0)
-#define flush_tlb_mm(mm) __tlb_flush_mm_cond(mm)
#define flush_tlb_page(vma, addr) do { } while (0)
-#define flush_tlb_range(vma, start, end) __tlb_flush_mm_cond(mm)
-#define flush_tlb_kernel_range(start, end) __tlb_flush_mm(&init_mm)
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+ __tlb_flush_mm_cond(mm);
+}
+
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ __tlb_flush_mm_cond(vma->vm_mm);
+}
+
+static inline void flush_tlb_kernel_range(unsigned long start,
+ unsigned long end)
+{
+ __tlb_flush_mm(&init_mm);
+}
#endif /* _S390_TLBFLUSH_H */