Merge branch 'linux-2.6'

[linux-2.6] / include / asm-powerpc / reg_booke.h

diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 064405c207bf33753864c17ae7161e36afc52dc5..d3e8dd0fc738c6611b2410a4b6b18371c6a4aaf3 100644 (file)
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -123,16 +123,23 @@
 #define SPRN_SPEFSCR   0x200   /* SPE & Embedded FP Status & Control */
 #define SPRN_BBEAR     0x201   /* Branch Buffer Entry Address Register */
 #define SPRN_BBTAR     0x202   /* Branch Buffer Target Address Register */
+#define SPRN_ATB       0x20E   /* Alternate Time Base */
+#define SPRN_ATBL      0x20E   /* Alternate Time Base Lower */
+#define SPRN_ATBU      0x20F   /* Alternate Time Base Upper */
 #define SPRN_IVOR32    0x210   /* Interrupt Vector Offset Register 32 */
 #define SPRN_IVOR33    0x211   /* Interrupt Vector Offset Register 33 */
 #define SPRN_IVOR34    0x212   /* Interrupt Vector Offset Register 34 */
 #define SPRN_IVOR35    0x213   /* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36    0x214   /* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37    0x215   /* Interrupt Vector Offset Register 37 */
 #define SPRN_MCSRR0    0x23A   /* Machine Check Save and Restore Register 0 */
 #define SPRN_MCSRR1    0x23B   /* Machine Check Save and Restore Register 1 */
 #define SPRN_MCSR      0x23C   /* Machine Check Status Register */
 #define SPRN_MCAR      0x23D   /* Machine Check Address Register */
 #define SPRN_DSRR0     0x23E   /* Debug Save and Restore Register 0 */
 #define SPRN_DSRR1     0x23F   /* Debug Save and Restore Register 1 */
+#define SPRN_SPRG8     0x25C   /* Special Purpose Register General 8 */
+#define SPRN_SPRG9     0x25D   /* Special Purpose Register General 9 */
 #define SPRN_MAS0      0x270   /* MMU Assist Register 0 */
 #define SPRN_MAS1      0x271   /* MMU Assist Register 1 */
 #define SPRN_MAS2      0x272   /* MMU Assist Register 2 */
@@ -140,15 +147,18 @@
 #define SPRN_MAS4      0x274   /* MMU Assist Register 4 */
 #define SPRN_MAS5      0x275   /* MMU Assist Register 5 */
 #define SPRN_MAS6      0x276   /* MMU Assist Register 6 */
-#define SPRN_MAS7      0x3b0   /* MMU Assist Register 7 */
 #define SPRN_PID1      0x279   /* Process ID Register 1 */
 #define SPRN_PID2      0x27A   /* Process ID Register 2 */
 #define SPRN_TLB0CFG   0x2B0   /* TLB 0 Config Register */
 #define SPRN_TLB1CFG   0x2B1   /* TLB 1 Config Register */
+#define SPRN_EPR       0x2BE   /* External Proxy Register */
 #define SPRN_CCR1      0x378   /* Core Configuration Register 1 */
 #define SPRN_ZPR       0x3B0   /* Zone Protection Register (40x) */
+#define SPRN_MAS7      0x3B0   /* MMU Assist Register 7 */
 #define SPRN_MMUCR     0x3B2   /* MMU Control Register */
 #define SPRN_CCR0      0x3B3   /* Core Configuration Register 0 */
+#define SPRN_EPLC      0x3B3   /* External Process ID Load Context */
+#define SPRN_EPSC      0x3B4   /* External Process ID Store Context */
 #define SPRN_SGR       0x3B9   /* Storage Guarded Register */
 #define SPRN_DCWR      0x3BA   /* Data Cache Write-thru Register */
 #define SPRN_SLER      0x3BB   /* Little-endian real mode */
@@ -159,6 +169,7 @@
 #define SPRN_L1CSR0    0x3F2   /* L1 Cache Control and Status Register 0 */
 #define SPRN_L1CSR1    0x3F3   /* L1 Cache Control and Status Register 1 */
 #define SPRN_PIT       0x3DB   /* Programmable Interval Timer */
+#define SPRN_BUCSR     0x3F5   /* Branch Unit Control and Status */
 #define SPRN_DCCR      0x3FA   /* Data Cache Cacheability Register */
 #define SPRN_ICCR      0x3FB   /* Instruction Cache Cacheability Register */
 #define SPRN_SVR       0x3FF   /* System Version Register */
@@ -223,7 +234,6 @@
 #define MCSR_ICPERR    0x40000000UL /* I-Cache Parity Error */
 #define MCSR_DCP_PERR  0x20000000UL /* D-Cache Push Parity Error */
 #define MCSR_DCPERR    0x10000000UL /* D-Cache Parity Error */
-#define MCSR_GL_CI     0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
 #define MCSR_BUS_IAERR         0x00000080UL /* Instruction Address Error */
 #define MCSR_BUS_RAERR         0x00000040UL /* Read Address Error */
 #define MCSR_BUS_WAERR         0x00000020UL /* Write Address Error */
@@ -232,6 +242,12 @@
 #define MCSR_BUS_WBERR         0x00000004UL /* Write Data Bus Error */
 #define MCSR_BUS_IPERR         0x00000002UL /* Instruction parity Error */
 #define MCSR_BUS_RPERR         0x00000001UL /* Read parity Error */
+
+/* e500 parts may set unused bits in MCSR; mask these off */
+#define MCSR_MASK      (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
+                       MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
+                       MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
+                       MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
 #endif
 #ifdef CONFIG_E200
 #define MCSR_MCP       0x80000000UL /* Machine Check Input Pin */
@@ -243,6 +259,11 @@
 #define MCSR_BUS_DRERR         0x00000008UL /* Read Bus Error on data load */
 #define MCSR_BUS_WRERR         0x00000004UL /* Write Bus Error on buffered
                                        store or cache line push */
+
+/* e200 parts may set unused bits in MCSR; mask these off */
+#define MCSR_MASK      (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
+                       MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
+                       MCSR_BUS_WRERR)
 #endif
 
 /* Bit definitions for the DBSR. */
@@ -283,7 +304,7 @@
 #define ESR_IMCB       0x20000000      /* Instr. Machine Check - Bus error */
 #define ESR_IMCT       0x10000000      /* Instr. Machine Check - Timeout */
 #define ESR_PIL                0x08000000      /* Program Exception - Illegal */
-#define ESR_PPR                0x04000000      /* Program Exception - Priveleged */
+#define ESR_PPR                0x04000000      /* Program Exception - Privileged */
 #define ESR_PTR                0x02000000      /* Program Exception - Trap */
 #define ESR_FP         0x01000000      /* Floating Point Operation */
 #define ESR_DST                0x00800000      /* Storage Exception - Data miss */