[PATCH] x86: Some preparationary cleanup for stack trace

[linux-2.6] / include / asm-powerpc / reg.h

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 0257189d5017e967f3fc5168606d772c73bf5c32..3a9fcc15811b44dff427a5b9fcbf52d48f18b4c8 100644 (file)
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -93,8 +93,8 @@
 #define MSR_LE         __MASK(MSR_LE_LG)       /* Little Endian */
 
 #ifdef CONFIG_PPC64
-#define MSR_           MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
-#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
+#define MSR_           MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
+#define MSR_KERNEL      MSR_ | MSR_SF
 
 #define MSR_USER32     MSR_ | MSR_PR | MSR_EE
 #define MSR_USER64     MSR_USER32 | MSR_SF
@@ -386,6 +386,8 @@
 #define   SRR1_WAKEMT          0x00280000 /* mtctrl */
 #define   SRR1_WAKEDEC         0x00180000 /* Decrementer interrupt */
 #define   SRR1_WAKETHERM       0x00100000 /* Thermal management interrupt */
+#define SPRN_HSRR0     0x13A   /* Save/Restore Register 0 */
+#define SPRN_HSRR1     0x13B   /* Save/Restore Register 1 */
 
 #ifndef SPRN_SVR
 #define SPRN_SVR       0x11E   /* System Version Register */
@@ -443,6 +445,10 @@
 #define   MMCRA_SIHV   0x10000000UL /* state of MSR HV when SIAR set */
 #define   MMCRA_SIPR   0x08000000UL /* state of MSR PR when SIAR set */
 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
+#define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
+#define   POWER6_MMCRA_THRM    0x00000020UL
+#define   POWER6_MMCRA_OTHER   0x0000000EUL
 #define SPRN_PMC1      787
 #define SPRN_PMC2      788
 #define SPRN_PMC3      789
@@ -495,6 +501,19 @@
 #define MMCR0_PMC2_LOADMISSTIME        0x5
 #endif
 
+/*
+ * An mtfsf instruction with the L bit set. On CPUs that support this a
+ * full 64bits of FPSCR is restored and on other CPUs it is ignored.
+ *
+ * Until binutils gets the new form of mtfsf, hardwire the instruction.
+ */
+#ifdef CONFIG_PPC64
+#define MTFSF_L(REG) \
+       .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
+#else
+#define MTFSF_L(REG)   mtfsf   0xff, (REG)
+#endif
+
 /* Processor Version Register (PVR) field extraction */
 
 #define PVR_VER(pvr)   (((pvr) >>  16) & 0xFFFF)       /* Version field */
@@ -573,6 +592,7 @@
 #define PV_630p        0x0041
 #define PV_970MP       0x0044
 #define PV_BE          0x0070
+#define PV_PA6T                0x0090
 
 /*
  * Number of entries in the SLB. If this ever changes we should handle