powerpc: Add asm/syscall.h with the tracehook entry points

[linux-2.6] / include / asm-powerpc / pgtable-ppc32.h

diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
index 11eede4a2906d43f8a46105d41106dc8bd2c13f6..6fe39e327047d16814f345402303efb75e9822b7 100644 (file)
--- a/include/asm-powerpc/pgtable-ppc32.h
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -295,10 +295,10 @@ extern int icache_44x_need_flush;
 #define _PAGE_PRESENT  0x00001 /* S: PTE contains a translation */
 #define _PAGE_USER     0x00002 /* S: User page (maps to UR) */
 #define _PAGE_FILE     0x00002 /* S: when !present: nonlinear file mapping */
-#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
-#define _PAGE_HWWRITE  0x00008 /* H: Dirty & RW, set in exception */
-#define _PAGE_RW       0x00010 /* S: Write permission */
-#define _PAGE_HWEXEC   0x00020 /* H: UX permission */
+#define _PAGE_RW       0x00004 /* S: Write permission (SW) */
+#define _PAGE_DIRTY    0x00008 /* S: Page dirty */
+#define _PAGE_HWEXEC   0x00010 /* H: SX permission */
+#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
 
 #define _PAGE_ENDIAN   0x00040 /* H: E bit */
 #define _PAGE_GUARDED  0x00080 /* H: G bit */
@@ -307,21 +307,14 @@ extern int icache_44x_need_flush;
 #define _PAGE_WRITETHRU        0x00400 /* H: W bit */
 
 #ifdef CONFIG_PTE_64BIT
-#define _PAGE_DIRTY    0x08000 /* S: Page dirty */
-
 /* ERPN in a PTE never gets cleared, ignore it */
 #define _PTE_NONE_MASK 0xffffffffffff0000ULL
-#else
-#define _PAGE_DIRTY    0x00800 /* S: Page dirty */
 #endif
 
 #define _PMD_PRESENT   0
 #define _PMD_PRESENT_MASK (PAGE_MASK)
 #define _PMD_BAD       (~PAGE_MASK)
 
-/* Until my rework is finished, FSL BookE still needs atomic PTE updates */
-#define PTE_ATOMIC_UPDATES     1
-
 #elif defined(CONFIG_8xx)
 /* Definitions for 8xx embedded chips. */
 #define _PAGE_PRESENT  0x0001  /* Page is valid */
@@ -402,6 +395,15 @@ extern int icache_44x_need_flush;
 #ifndef _PAGE_EXEC
 #define _PAGE_EXEC     0
 #endif
+#ifndef _PAGE_ENDIAN
+#define _PAGE_ENDIAN   0
+#endif
+#ifndef _PAGE_COHERENT
+#define _PAGE_COHERENT 0
+#endif
+#ifndef _PAGE_WRITETHRU
+#define _PAGE_WRITETHRU        0
+#endif
 #ifndef _PMD_PRESENT_MASK
 #define _PMD_PRESENT_MASK      _PMD_PRESENT
 #endif
@@ -412,6 +414,12 @@ extern int icache_44x_need_flush;
 
 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 
+
+#define PAGE_PROT_BITS __pgprot(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
+                                _PAGE_WRITETHRU | _PAGE_ENDIAN | \
+                                _PAGE_USER | _PAGE_ACCESSED | \
+                                _PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
+                                _PAGE_EXEC | _PAGE_HWEXEC)
 /*
  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
@@ -545,6 +553,10 @@ static inline pte_t pte_mkyoung(pte_t pte) {
        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 static inline pte_t pte_mkspecial(pte_t pte) {
        return pte; }
+static inline unsigned long pte_pgprot(pte_t pte)
+{
+       return __pgprot(pte_val(pte)) & PAGE_PROT_BITS;
+}
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
@@ -624,7 +636,7 @@ static inline unsigned long long pte_update(pte_t *p,
        : "cc" );
 #else /* PTE_ATOMIC_UPDATES */
        unsigned long long old = pte_val(*p);
-       *p = __pte((old & ~clr) | set);
+       *p = __pte((old & ~(unsigned long long)clr) | set);
 #endif /* !PTE_ATOMIC_UPDATES */
 
 #ifdef CONFIG_44x