#define _ASM_POWERPC_PCI_BRIDGE_H
#ifdef __KERNEL__
-#ifndef CONFIG_PPC64
-#include <linux/ioport.h>
#include <linux/pci.h>
+#include <linux/list.h>
+#include <linux/ioport.h>
+
+#ifndef CONFIG_PPC64
struct device_node;
struct pci_controller;
-/* Allocate a new PCI host bridge structure */
-extern struct pci_controller* pcibios_alloc_controller(void);
-
-/* Get the PCI host controller for a bus */
-extern struct pci_controller* pci_bus_to_hose(int bus);
-
/*
* Structure of a PCI controller (host bridge)
*/
struct pci_controller {
struct pci_bus *bus;
+ char is_dynamic;
void *arch_data;
- struct pci_controller *next;
+ struct list_head list_node;
struct device *parent;
int first_busno;
* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
* to determine which bus number to match on when generating type0
* config cycles
+ * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
+ * hanging if we don't have link and try to do config cycles to
+ * anything but the PHB. Only allow talking to the PHB if this is
+ * set.
+ * BIG_ENDIAN - cfg_addr is a big endian register
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
+#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
+#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem
return bus->sysdata;
}
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+ /* No specific ISA handling on ppc32 at this stage, it
+ * all goes through PCI
+ */
+ return 0;
+}
+
/* These are used for config access before all the PCI probing
has been done. */
int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
int where, u32 val);
-extern void setup_indirect_pci_nomap(struct pci_controller* hose,
- void __iomem *cfg_addr, void __iomem *cfg_data);
+extern int early_find_capability(struct pci_controller *hose, int bus,
+ int dev_fn, int cap);
+
extern void setup_indirect_pci(struct pci_controller* hose,
- u32 cfg_addr, u32 cfg_data);
+ u32 cfg_addr, u32 cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose);
+extern void __init update_bridge_resource(struct pci_dev *dev,
+ struct resource *res);
#else
-#include <linux/pci.h>
-#include <linux/list.h>
/*
* This program is free software; you can redistribute it and/or
return PCI_DN(busdn)->phb;
}
-extern struct pci_controller *
-pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void isa_bridge_find_early(struct pci_controller *hose);
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+ /* Check if address hits the reserved legacy IO range */
+ unsigned long ea = (unsigned long)address;
+ return ea >= ISA_IO_BASE && ea < ISA_IO_END;
+}
+
extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);
pci_process_bridge_OF_ranges(struct pci_controller *hose,
struct device_node *dev, int primary);
+/* Allocate a new PCI host bridge structure */
+extern struct pci_controller *
+pcibios_alloc_controller(struct device_node *dev);
#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
+extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
return (unsigned long)-1;
}
+static inline int pcibios_vaddr_is_ioport(void __iomem *address)
+{
+ return 0;
+}
#endif