#ifndef __ASM_PARISC_PCI_H
#define __ASM_PARISC_PCI_H
-#include <linux/config.h>
#include <asm/scatterlist.h>
*/
#define PCI_MAX_BUSSES 256
+
+/* To be used as: mdelay(pci_post_reset_delay);
+ *
+ * post_reset is the time the kernel should stall to prevent anyone from
+ * accessing the PCI bus once #RESET is de-asserted.
+ * PCI spec somewhere says 1 second but with multi-PCI bus systems,
+ * this makes the boot time much longer than necessary.
+ * 20ms seems to work for all the HP PCI implementations to date.
+ */
+#define pci_post_reset_delay 50
+
+
/*
** pci_hba_data (aka H2P_OBJECT in HP/UX)
**
/*
** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses.
-** See pcibios.c for more conversions used by Generic PCI code.
+** See pci.c for more conversions used by Generic PCI code.
+**
+** Platform characteristics/firmware guarantee that
+** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO
+** (2) PA_VIEW == IO_VIEW for GMMIO
*/
#define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \
? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \
: (a)) /* GMMIO */
-#define PCI_HOST_ADDR(hba,a) ((a) + hba->lmmio_space_offset)
+#define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \
+ ? (a) + hba->lmmio_space_offset \
+ : (a))
#else /* !CONFIG_64BIT */
*/
extern struct pci_port_ops *pci_port;
extern struct pci_bios_ops *pci_bios;
-extern int pci_post_reset_delay; /* delay after de-asserting #RESET */
-extern int pci_hba_count;
-extern struct pci_hba_data *parisc_pci_hba[];
#ifdef CONFIG_PCI
extern void pcibios_register_hba(struct pci_hba_data *);
{
}
+static inline void pcibios_penalize_isa_irq(int irq, int active)
+{
+ /* We don't need to penalize isa irq's */
+}
+
#endif /* __ASM_PARISC_PCI_H */