#include <linux/linkage.h>
#include <asm/hazards.h>
+#include <asm/war.h>
/*
* The following macros are especially useful for __asm__
#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
+#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
+
+
/*
* Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
*/
*/
#define __read_64bit_c0_split(source, sel) \
({ \
- unsigned long long val; \
- unsigned long flags; \
+ unsigned long long __val; \
+ unsigned long __flags; \
\
- local_irq_save(flags); \
+ local_irq_save(__flags); \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
- : "=r" (val)); \
+ : "=r" (__val)); \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
- : "=r" (val)); \
- local_irq_restore(flags); \
+ : "=r" (__val)); \
+ local_irq_restore(__flags); \
\
- val; \
+ __val; \
})
#define __write_64bit_c0_split(source, sel, val) \
do { \
- unsigned long flags; \
+ unsigned long __flags; \
\
- local_irq_save(flags); \
+ local_irq_save(__flags); \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: : "r" (val)); \
- local_irq_restore(flags); \
+ local_irq_restore(__flags); \
} while (0)
#define read_c0_index() __read_32bit_c0_register($0, 0)
static inline void tlb_read(void)
{
+#if MIPS34K_MISSED_ITLB_WAR
+ int res = 0;
+
+ __asm__ __volatile__(
+ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ " .set mips32r2 \n"
+ " .word 0x41610001 # dvpe $1 \n"
+ " move %0, $1 \n"
+ " ehb \n"
+ " .set pop \n"
+ : "=r" (res));
+
+ instruction_hazard();
+#endif
+
__asm__ __volatile__(
".set noreorder\n\t"
"tlbr\n\t"
".set reorder");
+
+#if MIPS34K_MISSED_ITLB_WAR
+ if ((res & _ULCAST_(1)))
+ __asm__ __volatile__(
+ " .set push \n"
+ " .set noreorder \n"
+ " .set noat \n"
+ " .set mips32r2 \n"
+ " .word 0x41600021 # evpe \n"
+ " ehb \n"
+ " .set pop \n");
+#endif
}
static inline void tlb_write_indexed(void)