struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
-#if defined(CONFIG_MIPS_MT_SMTC)
+ int srsets; /* Shadow register sets */
+ int core; /* physical core number */
+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered
* to be a "CPU" for the purposes of scheduling, but
* to all TCs within the same VPE.
*/
int vpe_id; /* Virtual Processor number */
+#endif
+#ifdef CONFIG_MIPS_MT_SMTC
int tc_id; /* Thread Context number */
-#endif /* CONFIG_MIPS_MT */
+#endif
void *data; /* Additional data */
} __attribute__((aligned(SMP_CACHE_BYTES)));