#include <asm/cache.h>
-#ifdef CONFIG_SGI_IP27
-#include <asm/sn/types.h>
-#endif
-
/*
* Descriptor for a cache
*/
struct cpuinfo_mips {
unsigned long udelay_val;
unsigned long asid_cache;
-#if defined(CONFIG_SGI_IP27)
-// cpuid_t p_cpuid; /* PROM assigned cpuid */
- cnodeid_t p_nodeid; /* my node ID in compact-id-space */
- nasid_t p_nasid; /* my node ID in numa-as-id-space */
- unsigned char p_slice; /* Physical position on node board */
-#endif
-#if 0
- unsigned long loops_per_sec;
- unsigned long ipi_count;
- unsigned long irq_attempt[NR_IRQS];
- unsigned long smp_local_irq_count;
- unsigned long prof_multiplier;
- unsigned long prof_counter;
-#endif
/*
* Capability and feature descriptor structure for MIPS CPU
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
+ int srsets; /* Shadow register sets */
+ int core; /* physical core number */
#if defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered
* to all TCs within the same VPE.
*/
int vpe_id; /* Virtual Processor number */
- int tc_id; /* Thread Context number */
#endif /* CONFIG_MIPS_MT */
+#ifdef CONFIG_MIPS_MT_SMTC
+ int tc_id; /* Thread Context number */
+#endif
void *data; /* Additional data */
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern void cpu_probe(void);
extern void cpu_report(void);
+extern const char *__cpu_name[];
+#define cpu_name_string() __cpu_name[smp_processor_id()]
+
#endif /* __ASM_CPU_INFO_H */