/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
-#define smp_mb__before_clear_bit() smp_mb()
-#define smp_mb__after_clear_bit() smp_mb()
+#define smp_mb__before_clear_bit() smp_llsc_mb()
+#define smp_mb__after_clear_bit() smp_llsc_mb()
/*
* set_bit - Atomically set a bit in memory
static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+ unsigned short bit = nr & SZLONG_MASK;
unsigned long temp;
if (cpu_has_llsc && R10000_LLSC_WAR) {
" beqzl %0, 1b \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+ : "ir" (1UL << bit), "m" (*m));
#ifdef CONFIG_CPU_MIPSR2
- } else if (__builtin_constant_p(nr)) {
+ } else if (__builtin_constant_p(bit)) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # set_bit \n"
" " __INS "%0, %4, %2, 1 \n"
"2: b 1b \n"
" .previous \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0));
+ : "ir" (bit), "m" (*m), "r" (~0));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (cpu_has_llsc) {
__asm__ __volatile__(
" .previous \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+ : "ir" (1UL << bit), "m" (*m));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
unsigned long flags;
a += nr >> SZLONG_LOG;
- mask = 1UL << (nr & SZLONG_MASK);
- local_irq_save(flags);
+ mask = 1UL << bit;
+ raw_local_irq_save(flags);
*a |= mask;
- local_irq_restore(flags);
+ raw_local_irq_restore(flags);
}
}
static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+ unsigned short bit = nr & SZLONG_MASK;
unsigned long temp;
if (cpu_has_llsc && R10000_LLSC_WAR) {
" beqzl %0, 1b \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+ : "ir" (~(1UL << bit)), "m" (*m));
#ifdef CONFIG_CPU_MIPSR2
- } else if (__builtin_constant_p(nr)) {
+ } else if (__builtin_constant_p(bit)) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # clear_bit \n"
" " __INS "%0, $0, %2, 1 \n"
"2: b 1b \n"
" .previous \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (nr & SZLONG_MASK), "m" (*m));
+ : "ir" (bit), "m" (*m));
#endif /* CONFIG_CPU_MIPSR2 */
} else if (cpu_has_llsc) {
__asm__ __volatile__(
" .previous \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+ : "ir" (~(1UL << bit)), "m" (*m));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
unsigned long flags;
a += nr >> SZLONG_LOG;
- mask = 1UL << (nr & SZLONG_MASK);
- local_irq_save(flags);
+ mask = 1UL << bit;
+ raw_local_irq_save(flags);
*a &= ~mask;
- local_irq_restore(flags);
+ raw_local_irq_restore(flags);
}
}
*/
static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
{
+ unsigned short bit = nr & SZLONG_MASK;
+
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
" beqzl %0, 1b \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+ : "ir" (1UL << bit), "m" (*m));
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
" .previous \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m)
- : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+ : "ir" (1UL << bit), "m" (*m));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
unsigned long flags;
a += nr >> SZLONG_LOG;
- mask = 1UL << (nr & SZLONG_MASK);
- local_irq_save(flags);
+ mask = 1UL << bit;
+ raw_local_irq_save(flags);
*a ^= mask;
- local_irq_restore(flags);
+ raw_local_irq_restore(flags);
}
}
static inline int test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
+ unsigned short bit = nr & SZLONG_MASK;
+ unsigned long res;
+
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
" .set mips3 \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+ : "r" (1UL << bit), "m" (*m)
: "memory");
-
- return res != 0;
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .previous \n"
" .set pop \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+ : "r" (1UL << bit), "m" (*m)
: "memory");
-
- return res != 0;
} else {
volatile unsigned long *a = addr;
unsigned long mask;
- int retval;
unsigned long flags;
a += nr >> SZLONG_LOG;
- mask = 1UL << (nr & SZLONG_MASK);
- local_irq_save(flags);
- retval = (mask & *a) != 0;
+ mask = 1UL << bit;
+ raw_local_irq_save(flags);
+ res = (mask & *a);
*a |= mask;
- local_irq_restore(flags);
-
- return retval;
+ raw_local_irq_restore(flags);
}
- smp_mb();
+ smp_llsc_mb();
+
+ return res != 0;
}
/*
static inline int test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
+ unsigned short bit = nr & SZLONG_MASK;
+ unsigned long res;
+
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
" .set mips3 \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+ : "r" (1UL << bit), "m" (*m)
: "memory");
-
- return res != 0;
#ifdef CONFIG_CPU_MIPSR2
} else if (__builtin_constant_p(nr)) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
"1: " __LL "%0, %1 # test_and_clear_bit \n"
"2: b 1b \n"
" .previous \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "ri" (nr & SZLONG_MASK), "m" (*m)
+ : "ri" (bit), "m" (*m)
: "memory");
-
- return res;
#endif
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .previous \n"
" .set pop \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+ : "r" (1UL << bit), "m" (*m)
: "memory");
-
- return res != 0;
} else {
volatile unsigned long *a = addr;
unsigned long mask;
- int retval;
unsigned long flags;
a += nr >> SZLONG_LOG;
- mask = 1UL << (nr & SZLONG_MASK);
- local_irq_save(flags);
- retval = (mask & *a) != 0;
+ mask = 1UL << bit;
+ raw_local_irq_save(flags);
+ res = (mask & *a);
*a &= ~mask;
- local_irq_restore(flags);
-
- return retval;
+ raw_local_irq_restore(flags);
}
- smp_mb();
+ smp_llsc_mb();
+
+ return res != 0;
}
/*
static inline int test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
+ unsigned short bit = nr & SZLONG_MASK;
+ unsigned long res;
+
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
" .set mips3 \n"
" and %2, %0, %3 \n"
" .set mips0 \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+ : "r" (1UL << bit), "m" (*m)
: "memory");
-
- return res != 0;
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
- unsigned long temp, res;
+ unsigned long temp;
__asm__ __volatile__(
" .set push \n"
" .previous \n"
" .set pop \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
- : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+ : "r" (1UL << bit), "m" (*m)
: "memory");
-
- return res != 0;
} else {
volatile unsigned long *a = addr;
- unsigned long mask, retval;
+ unsigned long mask;
unsigned long flags;
a += nr >> SZLONG_LOG;
- mask = 1UL << (nr & SZLONG_MASK);
- local_irq_save(flags);
- retval = (mask & *a) != 0;
+ mask = 1UL << bit;
+ raw_local_irq_save(flags);
+ res = (mask & *a);
*a ^= mask;
- local_irq_restore(flags);
-
- return retval;
+ raw_local_irq_restore(flags);
}
- smp_mb();
+ smp_llsc_mb();
+
+ return res != 0;
}
#include <asm-generic/bitops/non-atomic.h>